32b RISC/DSP media processor: MediaDSP3201

Shi, Ce; Wang, Weidong; Zhou, Li; Gao, Lei; Liu, Peng; Yao, Qingdong

doi:10.1117/12.586072

Cited by 4 publications

(6 citation statements)

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“…While operating the processor then priority will be given to the multiple generation bits. According to table multiplier bits will be generated, this process will be done in the internal Architecture of the processor [5] .…”

Section: Hard Multiples Problemmentioning

confidence: 99%

A Novel VLSI Architecture of Multiplier on Radix 4 using Redundant Binary Technique

Sriharish¹,

Kamaraju²

2014

IJCA

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The work mainly deals with in improving multiplication process by using Redundant Binary Technique. By implementing the existing method of Multiplication and Accumulation structure in Real time applications, occurs some difficulties like some hard multiples, and getting partial products in multiplication stage, it was not useful for higher radix values. The covalent redundant binary booth encoding algorithm overcomes the hard multiple generation problem and it reduces the partial products. The proposed algorithm dumped into the Booth encoding partial product generation stage. In this stage first step is to change the normal binary to redundant binary to make simple to avoid hard multiples. The partial products also reduce in the same stage. The method is implemented in the Fast Fourier Transform, Digital signal processors, and in Arithmetic logic unit. Finally the output results acquired for this method is number of gates are reduced and partial products are reduced up to 32 for 128 bit processor.

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Section: Hard Multiples Problemmentioning

confidence: 99%

A Novel VLSI Architecture of Multiplier on Radix 4 using Redundant Binary Technique

Sriharish¹,

Kamaraju²

2014

IJCA

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“…The RB correction vector incurs additional hardware for its accumulation. It can even increase the number of stages of the summing tree, if the word length of the multiplier is exactly , such as the 8-b and 16-b multipliers in application-specific data paths of multimedia and wireless applications [5], [6], and the multipliers for single extended and double extended floating point numbers, whose effective mantissa are 32 and 64 b, respectively [1]. Consequently, the power dissipation and worst case delay are also degraded by the inclusion of this correction vector.…”

Section: Sincementioning

confidence: 99%

“…T HE digital multiplier is a ubiquitous arithmetic unit in microprocessors, digital signal processors, and emerging media processors [1]- [4]. It is also a kernel operator in application-specific data path of video and audio codecs, digital filters, computer graphics, and embedded systems [5]- [8].…”

Section: Introductionmentioning

confidence: 99%

“…As 8-, 16-, 32-, and 64-b operands are pervasively used in application-specific data paths and multimedia and very long instruction word (VLIW) processors [1], [2], [5]- [8], [18], this paper focuses on power-of-two word-length RB multipliers to exploit the binary logarithmic partial product reduction rate of the RBA summing tree. By scrutinizing the overheads of existing Booth encoding algorithms, the notion of covalent redundant binary Booth encoding was briefly introduced in [19].…”

Section: Introductionmentioning

confidence: 99%

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A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

Chang

2009

IEEE Trans. Circuits Syst. I

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“…The experimental platform integrates one 32-bit integer RISC core -RISC32E [10] and eight 32-bit integer DSPs -MediaDSP3200 [11][12]. A 3x3 mesh topology NoC connects them and the DMA engine is also included.…”

Section: Evaluation Methodologymentioning

confidence: 99%

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

Yang

Wu³

et al. 2011

Lecture Notes in Computer Science

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Abstract. How to manage the message passing among inter processor cores with lower overhead is a great challenge when the multi-core system is the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. Generally speaking, the networks-on-chip connects the distributed multi-core system. It takes charge of message passing which including data and synchronization message among cores. The size of most data transmission is typically large enough that it remains strongly bandwidth-bound. The synchronization message is very small which is primarily latency bound. Thus the separated networks-on-chip are needed to transmit the above two types of message. In this paper we focus on the network for the transmission of synchronization messages. A hardware module -message passing unit (MPU) is proposed to manage the synchronization message passing for the heterogeneous multi-core system. Compared with the original single network approach, this solution reduces the run-time object scheduling and synchronization overhead effectively, thereby, improving the whole system performance.

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32b RISC/DSP media processor: MediaDSP3201

Cited by 4 publications

References 0 publications

A Novel VLSI Architecture of Multiplier on Radix 4 using Redundant Binary Technique

A Novel VLSI Architecture of Multiplier on Radix 4 using Redundant Binary Technique

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

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