32-GS/s SiGe Track-and-Hold Amplifier with 58-GHz Bandwidth and −64-dBc to −29-dBc HD3

Thomas, Philipp; Berroth, Manfred

doi:10.1109/icecs49266.2020.9294815

Cited by 2 publications

(3 citation statements)

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“…The performance values are summarized in Table I and compared with state-of-the-art track-and-hold circuits with an ultra-high bandwidth and sampling rate. Compared with [4], this implementation achieves double the sampling rate, a higher bandwidth and a max. HD3 value that is by 3 dB better for the same input voltage swing.…”

Section: Resultsmentioning

confidence: 99%

“…Differential amplifier stages steepen the edges of the clock signal, with one of them acting as a delay element for the SPA, and intermediate emitter follower buffers provide driving capability and level shifting. This architecture has shown valuable results, ranging from a 6.4-GS/s [2] and a 12.8-GS/s [3] chip for radar applications to a 32-GS/s circuit with 58-GHz bandwidth in [4]. Emitter follower buffers facilitate input and output matching with a differential 100 Ω resistance, as they exhibit a high input impedance, as well as a low output impedance around 5 Ω.…”

Section: Circuit Architecturementioning

confidence: 99%

“…Hence, we omit the second emitter follower output buffer in the track-and-hold core in comparison with other implementations. The SPA and SEF are linearized with subtractive gain composition and feedforward compensation, respectively, as in [4]. The subtractive branch increases the linear input range and the bandwidth of the SPA at the cost of a slightly reduced gain.…”

Section: Circuit Architecturementioning

confidence: 99%

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64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology

Thomas

Berroth

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Time-interleaving of energy-efficient data converter cores enables record symbol rates in electronic receivers. High-speed applications like optical data transmission or direct down-conversion in wireless mmWave receivers require ultra-high bandwidths and symbol rates, which CMOS data converters and especially their analog front ends cannot provide to date. We demonstrate a 64-GS/s track-and-hold circuit with a large-signal bandwidth of more than 61 GHz without any area-consuming peaking inductors, designed and manufactured in a 90-nm SiGe BiCMOS technology. The analog sampling front end exhibits a third harmonic distortion of -45 dBc to -32 dBc within the available frequency range of 50 GHz, which is better than the 5-bit requirement for 1.0-Vpp input signals. The ultra-high bandwidth of the circuit is twice as high as reported for CMOS data converters and in the range of broadband germanium photodiodes. This improves the bottleneck in hybrid integrated optoelectronic receiver front ends significantly. It is suited for time-interleaving of two channels with a doubled symbol rate of 128 GBaud, and the linearity allows to use it with 6-8-bit data converters.

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Section: Resultsmentioning

confidence: 99%

Section: Circuit Architecturementioning

confidence: 99%

Section: Circuit Architecturementioning

confidence: 99%

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