32*32 shared buffer type ATM switch VLSIs for B-ISDN

Sakurai, Y.; Matsubara, O.; Mizukami, M.; Uchida, M.; Sato, Y.; Asano, Kenichi

doi:10.1109/icc.1991.162454

Cited by 32 publications

(26 citation statements)

References 2 publications

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“…Once at the correct output, packets are simply sent, in turn, at every time slot. Shared output buffers [4], although they have no effect on the mean performance, reduce the buffer size needed to absorb queue-size variations and are used in this paper.…”

Section: A Input Versus Output Switch Modulesmentioning

confidence: 99%

“…For signaling, at every time slot, a queue sends an -bit message to the PA with the queue state, and the PA sends back a log -bit message with the selected packet subqueue [2]. This indicates the input-buffered switch has a compact and fast implementation compared to the more complex output-buffered switch [4].…”

Section: B Software (Sw) and Neural Network (Nn) Packet Arbitratorsmentioning

confidence: 99%

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A high-performance two-stage packet switch architecture

Brown

1999

IEEE Trans. Commun.

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Abstract-This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024 2 1024 switch size shows the simplest architecture has the best performance.Index Terms-Asynchronous transfer mode, neural networks, packet switching.

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Section: A Input Versus Output Switch Modulesmentioning

confidence: 99%

Section: B Software (Sw) and Neural Network (Nn) Packet Arbitratorsmentioning

confidence: 99%

A high-performance two-stage packet switch architecture

Brown

1999

IEEE Trans. Commun.

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“…ATLAS maintains multiple logical output queues as a shared pool of identifiers with a single shared controller, avoiding the high area cost of dedicated buffers and controllers per output queue, as in the Prizma switch [6]. In addition, the operation of the single controller in ATLAS I is pipelined, since it has to manage the cell data structures at much higher rates than previous switches [20] [11]. The ATLAS switch implements multilane credit-based flow control (section 2), while other switches either provide no flow control at all [6] [11] [20], or only single-lane flow control [18].…”

Section: Introductionmentioning

confidence: 99%

Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control

Kornaros¹,

Kozyrakis

Vatsolaki

et al.

Proceedings Seventeenth Conference on Advanced Research in VLSI

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ABSTRACT:We describe the queue management block of ATLAS I , a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3-and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM's, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special access

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“…It is now almost unanimously agreed that ATM will become an enabling technology for the future integrated digital networks and thus nearly all large computer and communication companies have invested in developing ATM products [2,3,4,5]. However, most existing ATM products have been developed without attention to a fundamental problem of the ATM: trac control to maintain a satisfactory network performance.…”

mentioning

confidence: 99%

“…In this way, lossless synchronous transmission is guaranteed. 3 Dynamic bandwidth sharing and lossless transmission Algorithm 2.1 would behave very much like STM or Stop-and-Go if no asynchronous transmission were allowed in Step 3. Each connection is allocated a certain amount of bandwidth, but any unused or unallocated bandwidth is wasted.…”

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confidence: 99%

An enhanced timed-round-robin traffic control scheme for ATM networks

Qin

Proceedings of LCN - 21st Annual Conference on Local Computer Networks

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ATM (asynchronous transfer mode) aims at providing both guaranteed bandwidth to support real-time communications and dynamic bandwidth sharing to accommodate bursty data traffic. Achievement of this goal is vital to make ATM an enabling technology for the future integrated digital networks. To realize this objective, good algorithms for controlling network traffic are required. This paper proposes a traffic control scheme which uses a timed-round-robin cell transmission scheduling algorithm enhanced with a simple feedback flow control mechanism to realize the promised advantages of ATM networks. Specifically, with the proposed scheme, a network is able to provide each user with (1) a guaranteed bandwidth, (2) immediate access to the full link bandwidth when there is no contention from other users, and (3) free of cell losses. An ATM switch design is also presented which shows the feasibility of implementing the proposed scheme with todayś switch architectures without adding much extra cost.This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of Mitsubishi Electric Research Laboratories, Inc.; an acknowledgment of the authors and individual contributions to the work; and all applicable portions of the copyright notice. Copying, reproduction, or republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Research Laboratories, Inc. All rights reserved. Abstract ATM (asynchronous transfer mode) aims at providing both guaranteed bandwidth to support real-time communications and dynamic bandwidth sharing to accommodate bursty data trac. Achievement of this goal is vital to make ATM an enabling technology for the future integrated digital networks. To realize this objective, good algorithms for controlling network trac are required. This paper proposes a trac control scheme which uses a timed-round-robin cell transmission scheduling algorithm enhanced with a simple feedback ow control mechanism to realize the promised advantages of ATM networks. Specically, with the proposed scheme, a network is able to provide each user with (1) a guaranteed bandwidth, (2) immediate access to the full link bandwidth when there is no contention from other users, and (3) free of cell losses. An ATM switch design is also presented which shows the feasibility of implementing the proposed scheme with today's switch architectures without adding much extra cost.

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32*32 shared buffer type ATM switch VLSIs for B-ISDN

Cited by 32 publications

References 2 publications

A high-performance two-stage packet switch architecture

A high-performance two-stage packet switch architecture

Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control

An enhanced timed-round-robin traffic control scheme for ATM networks

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