32/28nm Educational Design Kit: Capabilities, deployment and future

Goldman, Rich; Bartleson, Karen; Wood, Troy; Kranen, Kevin; Melikyan, Vazgen; Babayan, E.

doi:10.1109/primeasia.2013.6731222

Cited by 23 publications

(4 citation statements)

References 4 publications

(4 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We demonstrate the proposed optimization strategy in designing OpenSPARC T1 core, which is an open-source version of UltraSPARC processor. We first synthesized all modules and performed the placement and routing using Synopsys 32 nm EDK standard cell library [23]. We used Synopsys Design Compiler, IC Compiler, and Primetime for synthesizing, placement and routing, and static timing and power analysis, respectively [24,25,26].…”

Section: Optimization Strategies For the Proposed Nvffmentioning

confidence: 99%

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Park

Yim

2019

Micromachines

View full text Add to dashboard Cite

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is 6.9 % normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1 × and the energy by 1.5 × . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

show abstract

Section: Optimization Strategies For the Proposed Nvffmentioning

confidence: 99%

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Park

Yim

2019

Micromachines

View full text Add to dashboard Cite

show abstract

“…An ASIC was implemented in the SAED 28 nm process, an educational library provided by Synopsys [31]. The TX/RX buffer that stores A-Packets in the RTS layer is a large-sized memory of approximately 50 KB, and therefore, it is not provided in the Synopsys' Armenia Educational Department (SAED) 28 nm library, so it was excluded from the implementation.…”

Section: Resultsmentioning

confidence: 99%

Design and Implementation of an MIPI A-PHY Retransmission Layer for Automotive Applications

Shin,

Kang,

Kim

2023

Electronics

View full text Add to dashboard Cite

Recently, with the development of automobile technologies such as advanced driver assistance systems (ADASs), the performance and number of cameras and displays required for a vehicle have significantly increased. Therefore, the need for in-vehicle high-speed data transmission has increased, but there is difficulty in handling the required high-speed data transmission in existing in-vehicle networks. The MIPI A-PHY interface for automobiles has been proposed as a new standard to solve this issue. To ensure data transmission in noisy automotive environments, the A-PHY interface contains an added retransmission (RTS) layer within the new physical layer. In this paper, we propose and design in detail the structure of an RTS layer presented in the standard A-PHY interface. The proposed RTS layer was designed to satisfy the RTS specification of the MIPI A-PHY standard and was verified through simulations. Moreover, the A-PHY SerDes environment was configured in an FPGA using a Xilinx KC705 FPGA development board and an FPGA Mezzanine Card (FMC) loopback module, and RTS layer operation was verified through the process of transmitting video data to the A-Packet. The A-PHY interface with the RTS layer designed on the FPGA uses 3924 LUTs, 2019 registers, and 132 block memories and operates at a maximum speed of 200 MHz. In addition, as a result of designing the A-PHY interface as an ASIC implementation using the Synopsys SAED 28 nm process, the number of logic gates is 25 K, the chip area is 0.40 mm2, and the maximum operating speed is 200 MHz.

show abstract

“…A series of directed tests were written to verify the core functionality of the design. For synthesis and layout evaluation, we used the Synopsys 32 nm educational standard cell library [20]. We targeted a 1 ns clock period at nominal voltage of 1.05 V. All results are presented using the typical-typical corner at 25 C, and all timing and power results include post place and route parasitics.…”

Section: B Hardware Evaluationmentioning

confidence: 99%

SatIn: Hardware for Boolean Satisfiability Inference

Zhu¹,

C.²,

Wang³

et al. 2023

Preprint

View full text Add to dashboard Cite

This paper describes SatIn, a hardware accelerator for determining boolean satisfiability (SAT)-an important problem in many domains including verification, security analysis, and planning. SatIn is based on a distributed associative array which performs short, atomic operations that can be composed into high level operations. To overcome scaling limitations imposed by wire delay, we extended the algorithms used in software solvers to function efficiently on a distributed set of nodes communicating with message passing. A cycle-level simulation on real benchmarks shows that SatIn achieves an average 72x speedup against Glucose [1], the winner of 2016 SAT competition, with the potential to achieve a 113x speedup using two contexts. To quantify SatIn's physical requirements, we placed and routed a single clause using the Synopsys 32 nm educational development kit. We were able to meet a 1 ns cycle constraint with our target clause fitting in 4867 µm 2 and consuming 63.8 µW of dynamic power; with a network, this corresponds to 100k clauses consuming 8.3 W of dynamic power (not including leakage or global clock power) in a 500 mm 2 32 nm chip.

show abstract

32/28nm Educational Design Kit: Capabilities, deployment and future

Cited by 23 publications

References 4 publications

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Design and Implementation of an MIPI A-PHY Retransmission Layer for Automotive Applications

SatIn: Hardware for Boolean Satisfiability Inference

Contact Info

Product

Resources

About