30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Chau, R.; Kavalieros, J.; Roberds, B.; Schenker, Richard E.; Lionberger, D.; Barlage, Douglas W.; Doyle, B.S.; Arghavani, Reza; Murthy, A.; Dewey, G.

doi:10.1109/iedm.2000.904255

Cited by 89 publications

(62 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table I displays a selected number of electrical characteristics for devices with channel lengths between 15 nm and 36 nm. It is obvious from both, the transconductance data as well as the drive current values that our data compare well with state-of-the-art classical approaches [1], [2]. In contrast to the results from Kedzierski and co-workers [3] on thin body MOSFETs, our V-groove approach does not suffer from high source (or drain) to channel contact resistances.…”

Section: Resultscontrasting

confidence: 38%

“…This is the case when the channel length becomes comparable to the body thickness of the channel. Simulations of the impact of the body thickness in ultrasmall MOSFETs [9], suggest that significant 1 The effective channel width of the devices was found to decrease with increasing L . This is the case since the etch stop layer at the n =p -interface is not perfectly uniform.…”

Section: Resultsmentioning

confidence: 99%

“…Experimentalists have proven that aggressive scaling results in high performance devices in the sub-50 nm channel length regime [1]- [3]. The question of how far can MOSFET size scale-while obtaining improved device characteristics-remains open.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Sub-40 nm SOI V-groove n-MOSFETs

Appenzeller

Martel²,

Avouris³

et al. 2002

IEEE Electron Device Lett.

View full text Add to dashboard Cite

Abstract-We present output and transfer characteristics of single-gated, 36 nm, 46 nm and 56 nm channel length SOI MOSFETs with a V-groove design. For the shortest devices we find transconductances as high as 900 S m and drive currents of 490 A m at gs th = 0 6 V. The V-groove approach combines the advantages of a controlled, extremely abrupt doping profile between the highly doped source/drain and the undoped channel region with an excellent suppression of short-channel effects. In addition, our V-groove design has the potential of synthesizing devices in the 10 nm range.Index Terms-Single-gated device, SOI, ultrashort channel, V-groove MOSFET.

show abstract

Section: Resultscontrasting

confidence: 38%

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Sub-40 nm SOI V-groove n-MOSFETs

Appenzeller

Martel²,

Avouris³

et al. 2002

IEEE Electron Device Lett.

View full text Add to dashboard Cite

show abstract

“…Prototype 30-nm MOSFETs have already been developed [2], [3] for the 65-nm technology node expected in 2005 [4]. Trapping of a single carrier charge in defect states near the Si/SiO interface and the related local modulation in carrier density and/or mobility [5]- [7] in an area comparable with the characteristic device dimensions, will have a profound effect on the drain and gate current [8] in such MOSFETs.…”

mentioning

confidence: 99%

RTS amplitudes in decananometer MOSFETs: 3-D simulation study

Asenov

Balasubramaniam

Brown

et al. 2003

IEEE Trans. Electron Devices

256

181

View full text Add to dashboard Cite

“…Prototype MOSFETs with conventional architecture, gate length of 30 nm, and oxide thickness below 10 have already been successfully demonstrated [3]. In such devices, not only the discrete and random dopant charge [4]- [6], but also the atomic scale roughness of the Si/SiO and gate/SiO interfaces will introduce significant intrinsic parameter fluctuations.…”

Section: Introductionmentioning

confidence: 99%