30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS

Shahramian, Shahriar; Dehlaghi, Behzad; Liang, Joshua; Bespalko, Ryan; Dunwell, Dustin; Bailey, James; Wang, Bo; Sharif-Bakhtiar, Alireza; O'Farrell, Michael; Tang, Kerry; Carusone, Anthony Chan; Cassan, David; Tonietto, Davide

doi:10.1109/isscc.2019.8662421

Cited by 15 publications

(7 citation statements)

References 3 publications

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“…At higher data rates, ISI is more detrimental, requiring more sophisticated filters. Moreover, the optimization of equalizer coefficients is a non-trivial problem, often requiring an LMS or even a genetic search algorithm [1], [18]. These controllers are also becoming more complex, worsening the problem.…”

Section: B Equalizationmentioning

confidence: 99%

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2021

IEEE Open J. Circuits Syst.

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This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decisiondirected equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by 20dB per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system's ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system's ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.INDEX TERMS Adaptive equalization, clock and data recovery (CDR), decision-directed equalization, discrete multi-tone (DMT), orthogonal frequency division multiplexing (OFDM), SERDES, single-tap equalization, timing recovery, wireline. JEREMY COSSON-MARTIN (Graduate Student Member, IEEE) received the B.A.Sc. degree in electrical engineering from Queen's University, Kingston, ON, Canada, in the spring of 2018. In the fall of 2018, he began an M.A.Sc. program at the University of Toronto, ON, Canada, under the supervision of Prof. A. Sheikholeslami. In 2019, he transferred into a Ph.D. program.In the summer of 2018, he joined Huawei Canada, Toronto, ON, Canada, as an intern, where he was involved in creating in-lab measurement scripts for a prototype 56-Gb/s SerDes integrated chip. He also received experience in 7-nm FinFET layout. Currently, he is researching multi-tone schemes for ultra-high-speed wireline applications.

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Section: B Equalizationmentioning

confidence: 99%

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2021

IEEE Open J. Circuits Syst.

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“…A prototype of the proposed side-channel link is tested on a 7-nm FinFET 56 Gb/s PAM-4 transceiver from [2]. Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…In high-speed wireline communication links, limited channel bandwidth requires equalization in the transmitter (TX) and receiver (RX) to compensate for frequency-dependent loss [1]. Typically, the RX would employ adaptation algorithms to optimize their highly programmable equalizers to minimize bit error rate (BER) and power during operation [2], [3]. Highly programmable TXs are also available; however, without channel information, they can only be initialized to nominal settings at start-up, and cannot be dynamically adapted during operation [4].…”

Section: Introductionmentioning

confidence: 99%

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Zhang

Liang

Shahramian

et al. 2020

IEEE Solid-State Circuits Lett.

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A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver's conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 10 4 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.

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“…QA amplifier (N=32) quantization levels before and after the GA optimization for sinusoidal input when the SNDR is noise-limited ral selection. GAs have been applied in analog design for automated circuit synthesis [24], [25] and finding optimal circuit coefficients for wireline receiver analog front-ends [26]. Moreover, GAs have the advantage of not having to rely on assumptions about the performance landscape, which in this case varies considerably based on the operative scenario, especially for wireless applications.…”

Section: A the Genetic Algorithmmentioning

confidence: 99%

Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law

Yu¹,

Carusone

Liscidini

2022

IEEE Open J. Circuits Syst.

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Digital mismatch calibration for quantized analog (QA) signal processing is proposed for the first time. Since the proposed calibration mechanism does not require uniform QA slicer levels, non-uniform quantization can be applied to improve the system performance. We propose two methods utilizing the genetic algorithm and µ-law to find non-uniform slicer levels offering superior performance compared to uniform levels. Simulations show that for a QA amplifier consisting of 32 slices, the signal-to-noise-anddistortion ratio (SNDR) under a multitone input can be doubled by adjusting only the quantization levels while maintaining the same structure and same power, compared to uniform quantization levels that provide 54 dB of SNDR.

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30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS

Cited by 15 publications

References 3 publications

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law

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