3 Gbps, 5000 ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA

Aoyama, M.; Ogasawara, Kunio; Sugawara, Mariko; Ishibashi, Tadao; Shimoyama, S.; Yamaguchi, Koichi; Yanagita, T.; Noma, Tomohiro

doi:10.1109/vlsic.2003.1221175

Cited by 34 publications

(33 citation statements)

References 1 publication

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“…One of simplest ways to implement an SSCG is by using a phase interpolator (PI) to directly modulate the VCO clock into an SSC clock in a serializer-deserializer (SerDes) transmitter-receiver (TX-RX) [52][53][54][55][56]. However, this method introduces excessive cycle-to-cycle jitter caused by minimum phase step resolution, differential non-linearity (DNL) and integral non-linearity (INL).…”

Section: Sscg Architectures and Proposed New Designmentioning

confidence: 99%

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PLL performance comparison with application to spread spectrum clock generator design

Hsieh

Welch

Sobelman

2009

Analog Integr Circ Sig Process

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This paper presents performance, power and area comparisons of LC vs. Ring VCO-based PLL designs in order to determine the best option for high-speed spread spectrum clock generator (SSCG) designs. Analytical performance, power and area comparisons of LC versus Ring VCO-based PLL designs demonstrate that a Ring VCO can be used to meet the requirements of SATA and SAS applications at rates up to 6 Gbps. The designed SSCG operating frequency range is 2-4.25 GHz with RMS RJ jitter \1.3 and \1.5 pS for non-SSC and SSC modes, respectively, at 3 GHz. The measured EMI reduction is 18 and 21 dB for 2,300 and 4,600 ppm SSC, respectively, also at 3 GHz.

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Section: Sscg Architectures and Proposed New Designmentioning

confidence: 99%

“…The divider is held constant during the PLL operation. The use of the PI provides a smaller phase step shifting at the divider output compared to the designs in [52][53][54]. The small phase steps reduce the low frequency noise at the divider output, which leads to lower jitter.…”

Section: Sscg Architectures and Proposed New Designmentioning

confidence: 99%

PLL performance comparison with application to spread spectrum clock generator design

Hsieh

Welch

Sobelman

2009

Analog Integr Circ Sig Process

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“…If no clock is forwarded from a transmitter to a receiver like in PCI-Express (PCI-E), Serial-ATA (SATA), and Universal Serial Bus (USB), however, there can be non-zero frequency difference between the transmitter and the receiver clocks. Then the CDR circuit has to capable of tracking the phase and frequency difference between the transmitter and receiver [9]. For seamless phase rotation, analog phase interpolator is most widely used but its design is very complicated because the accuracy of the phase interpolation is heavily dependent on the slope of the input clock signals [10].…”

Section: Introductionmentioning

confidence: 99%

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Choi

Yoo

2014

IEICE Electron. Express

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A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10 !12 .

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“…SSC reduces the peak EMI emission by spreading the carrier frequency. EMI reduction techniques using SSC have been studied and explored for 1.5-/3.0-Gbps SATA [3,4]. However, it is more important to consider the timedomain impact of SSC on the receiver-side tracking skew since signal integrity, including jitter, is a critical concern in 6-Gbps SATA due to a reduced bittime.…”

Section: Introductionmentioning

confidence: 99%

A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver

Moon

2010

IEICE Electron. Express

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A transmitter-side spread-spectrum clock generator (TX-SSCG) with a second-order ΔΣ modulator is proposed for a 6-Gbps Serial ATA. Mixed-mode simulations show that a second-order ΔΣ modulator in TX-SSCG reduces the random jitter component of the receiver-side tracking skew through quantization noise shaping. Deterministic jitter is reduced with the loop bandwidth of RXPLL. A 0.13-μm CMOS prototype chip shows that the transceiver operates at 6 Gbps over an 8-m SATA cable in TX-SSCG on and off. With TX-SSCG on, the spectrum is down-spread with 11.7-dB peak reduction and 5000-ppm spread amount.

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3 Gbps, 5000 ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA

Cited by 34 publications

References 1 publication

PLL performance comparison with application to spread spectrum clock generator design

PLL performance comparison with application to spread spectrum clock generator design

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver

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