3-D interconnect capacitance calculation for multi-conductor and its application to a ROM circuit design

Abstract

The parasitic capacitance associated with interconnection lines has become increasingly important with the scaling down of both device dimension and interconnection line for the present VLSI or ULSI circuit design. A 2-D and a 3-D capacitance simulators have been developed for evaluating the parasitic capacitance in VLSI structures. The coupling capocitancc, cross-wiring capacitance, and thefringing capacitance between wires in a multi-layer structure have been studied. Application of the simulated interconnect capacitance to a ROM circuit shows that good match between simulation and experiments has been achieved. We have made extensions to study the scaling effect of a commercialized ROM circuit design, from which a density of twice the original memory cell size can be obtained by the same design rule.