3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI

Bassi, Matteo; Radice, Francesco; Bruccoleri, Melchiorre; Erba, Simone; Mazzanti, Andrea

doi:10.1109/isscc.2016.7417909

Cited by 35 publications

(6 citation statements)

References 3 publications

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“…The DAC should drive the wireline with sufficient swing, linearity, and bandwidth. The final stage can be implemented in two ways: utilizing a current-mode driver or employing a source-series-terminated (SST) driver, both of which are commonly seen in wireline TXs [42], [43]. The SST or voltage-mode DAC creates the output levels based on a voltage division between the effective output resistance of the DAC cells and the load.…”

Section: A 6-bit Current-steering Dacmentioning

confidence: 99%

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

Fakkel,

Mortazavi,

Overwater

et al. 2024

IEEE J. Solid-State Circuits

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Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (QEC) are necessary. However, QEC requires a large amount of data to be transferred from a cryogenic controller at 4 K to a classical processor at room temperature (RT). To bridge the gap, a high-speed data link between the quantum processor at CT and the classical counterpart at RT is needed. The proposed PAM4 TX architecture integrates a low-power 64:4 serializer structure, a high-speed 4:1 currentmode logic (CML) multiplexer, and a linear 6-bit digital-to-analog converter (DAC). Considering the challenges and benefits of CMOS operating at CTs, the TX architecture and circuitry are designed to exploit the maximum speed, while maintaining sufficient linearity. The fabricated 40-nm CMOS chip achieves a data rate of 40-Gb/s (36-Gb/s), an energy efficiency of 2.46 pJ/b (2.47 pJ/b), and 97.8% (96.6%) ratio of level mismatch (RLM) at CT (RT). While demonstrating an energy efficiency comparable to prior-art TXs in more advanced CMOS nodes at RT, the broad operating temperature of the proposed TX enables the required high-speed wireline link for large-scale quantum computers.

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Section: A 6-bit Current-steering Dacmentioning

confidence: 99%

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

Fakkel,

Mortazavi,

Overwater

et al. 2024

IEEE J. Solid-State Circuits

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“…Compared to not-return-to-zero (NRZ), PAM4 signals with half the Nyquist frequency have higher spectral efficiency, which is an attractive solution for high-speed links with severely bandwidthconstrained channels. However, the use of PAM4 modulation technology also brings great challenges to the design of transceivers [3]. In general, transmitters designed for PAM4 signaling must be able to provide higher swings because the corresponding receivers need to efficiently resolve smaller amplitudes compared to NRZ signaling.…”

Section: Figure 1 Overall Block Diagram Of the Transceivermentioning

confidence: 99%

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Liu

Wen

et al. 2023

Preprint

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To meet the demand of low bit error rate (BER) and high bandwidth for high-speed links, a reliable 112Gb/s four-level pulse amplitude modulation (PAM4) transceiver design scheme with adaptive threshold voltage and adaptive decision feedback equalizer (DFE) is proposed in this paper. In this scheme, three continuous time linear equalizers (CTLE) at the front end of receiver are used to compensate the high-frequency, mid-frequency and low-frequency signals respectively, and the variable gain amplifier (VGA) and saturation amplifier (SatAmp) are used to scale the signal amplitude. In addition to the three data samplers, four auxiliary samplers are also used for threshold adaptation. The sign-sign least mean squares algorithm uses the offset between the data sampler and the auxiliary sampler at the receiver side to drive the auxiliary reference voltage to converge to the signal constellation level, thus ensuring that the eye diagram of the PAM4 received signal has equal spacing and a constant signal-noise ratio (SNR) for the three eyes in the vertical direction. In addition, the adaptive DFE for PAM4 signaling allows the transceiver to better adapt to the channel and thus achieve better equalizer performance. The simulation results show that the PAM4 transceiver design can compensate up to 25dB of channel loss with an average eye height of 59.6 mv and an average eye width of 0.27 UI at a bit error rate of 10− 12 under the condition of 3 tap Feedforward equalizer (FFE) transmitter.

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“…Video chat software creates high demand on internet bandwidth, often resulting in poor video transmission (Rehn, 2017;Xu, Yu, Li, & Liu, 2012). This is especially true during times of high internet traffic, such as during the school day, where internet connection speeds can drop even further (Bassi, Radice, Bruccoleri, Erba, & Mazzanti, 2016). This problem was further exasperated by the Canadian university undergoing Wi-Fi upgrades, which slowed down the system (Pike, 2016).…”

Section: Barriers Of Technologymentioning

confidence: 99%

Overcoming Barriers for Implementing International Online Collaborative Assignments in Chemistry

et al. 2019

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Organic chemistry students at two universities, one in Canada and the other in the United States, connected using video conferencing software as learning partners for six online collaborative assignments. Mixed-methods analysis of interviews, surveys, and student-written reflections was used to identify barriers that students encountered during the international online collaborative assignments. Students described the barriers of their experience with online collaborative assignments in terms of course pedagogy or chemistry concepts, social interactions, and technology. Results were compared and supported by additional data sources. Students were successful at overcoming most barriers, demonstrating real-world problem-solving and a high degree of resiliency. Persistent barriers were identified and resolved by faculty through revisions to design and implementation.

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3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI

Cited by 35 publications

References 3 publications

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Overcoming Barriers for Implementing International Online Collaborative Assignments in Chemistry

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