3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Shibasaki, Takayuki; Danjo, Takumi; Ogata, Yudai; Sakai, Yoshihiro; Miyaoka, Hiroki; Terasawa, Futoshi; Kudo, Masahiro; Kano, H.; Matsuda, Atsushi; Kawai, S.; Arai, Tomomi; Higashi, Hirohito; Naka, Naoaki; Yamaguchi, Hisakatsu; Mori, Toshihiko; Koyanagi, Yoichi; Tamura, Hirotaka

doi:10.1109/isscc.2016.7417908

Cited by 51 publications

(9 citation statements)

References 2 publications

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“…Active power is estimated by multiplying the synthesized active energy numbers per atomic operation (Table II) with the count of each atomic operation obtained from our functional simulator and dividing the sum by running time. For multichip applications (CIFAR-10 CNN and ResNet), we assume 4.4pJ/bit for inter-chip I/O, based on state-of-the-art 56Gbps serial link on 28nm (same process as Shenjing) [8].…”

Section: System Level Resultsmentioning

confidence: 99%

Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

Wang¹,

Zhou²,

Wong³

et al. 2019

Preprint

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The next wave of on-device AI will likely require energy-efficient deep neural networks. Brain-inspired spiking neural networks (SNN) has been identified to be a promising candidate. Doing away with the need for multipliers significantly reduces energy. For on-device applications, besides computation, communication also incurs a significant amount of energy and time. In this paper, we propose Shenjing, a configurable SNN architecture which fully exposes all on-chip communications to software, enabling software mapping of SNN models with high accuracy at low power. Unlike prior SNN architectures like TrueNorth, Shenjing does not require any model modification and retraining for the mapping. We show that conventional artificial neural networks (ANN) such as multilayer perceptron, convolutional neural networks, as well as the latest residual neural networks can be mapped successfully onto Shenjing, realizing ANNs with SNN's energy efficiency. For the MNIST inference problem using a multilayer perceptron, we were able to achieve an accuracy of 96% while consuming just 1.26 mW using 10 Shenjing cores.

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Section: System Level Resultsmentioning

confidence: 99%

Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

Wang¹,

Zhou²,

Wong³

et al. 2019

Preprint

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“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

Section: Interconnectmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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“…as H ctle (s) = c 0 + c 1 s, the sampling phase as well as dLev itself). Note that sign d i sign e j corresponds to correlating the error made at a certain time with the bit received at possibly another time in the past or in the future, where obviously the latter can be considered only when data and errors are parallelized before computation of the fully-adaptive algorithm [8,17,27,[42][43][44]. Such correlations provide information on whether to increase or decrease the corresponding parameter c and bring it to convergence, and are usually collected and averaged over time [12,27].…”

Section: Including Fully-adaptive Equalizationmentioning

confidence: 99%

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

Menin¹,

Bernardi²,

Cortiula³

et al. 2020

Adv. sci. technol. eng. syst. j.

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We describe an efficient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model's complexity.

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3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Cited by 51 publications

References 2 publications

Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

Today’s computing challenges: opportunities for computer hardware design

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

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