3.3 V GPS receiver MMIC implemented on a mixed-signal, silicon bipolar array

Abstract

This generic GPS MMIC contains two downconversion stages and the dividers, buffers, digital phase-frequency detector and negative resistance cell required to synthesize both Los and a ITL system clock. The MMIC operates from a 20 MHz external reference and provides overall conversion gain of about 65 dB from a 1575 MHz RF to a 15 MHz second IF. The 1.8 x 1.8 mm MMIC is implemented on a mixed-signal, silicon bipolar cell array and consumes less than 150 mW from a single 3.3V supply.