29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

Recent Advances and Trends in High-Performance Embedded Data Converters

“…This is an alternative to ''time'' or ''code search'' parallelizations employed in flash, time-interleaved SAR and subranging converters, to sample the input signal and provide an output sample in every clock cycle. And, in fact, high-speed pipeline ADCs have been described [66].…”

“…see [66]) are frequently used in pipeline ADCs. But as explained in the previous sub-section, technology scaling is making it increasingly difficult to attain the high gain that is necessary to ensure proper performance of these converters.…”

“…The critical point is ensuring the settling is linear, because the situation is then equivalent to a gain error. This has been done in [92] to reduce power in the above mentioned open loop amplifier, and also in a very high frequency pipeline ADC using closed loop MDACs [66].…”

15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC

“…For example, timing skew of only 100fs for a 2×-interleaved ADC results in an SFDR of 76dB for a 500MHz input signal. Background calibration can track these mismatch artifacts [1] (as well as other ADC errors [2]), but incur a nonnegligible algorithm convergence time every time the ADC is enabled. In addition, interleaving increases production cost as it can result in larger die area.…”

“…This dithering approach reduces the available correction range and needs dither blocks in the first N-1 stages. However, the dither signal does not need to be digitally subtracted from the quantized input signal as is the case with DAC dither [2,5], which requires matching the dither's analog and digital path to prevent dither leakage. We obtain >5dB improvement in SFDR performance at room temperature, and more than >15dB at 125°C, as shown in the input amplitude sweeps of Fig.…”