28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications

Yang, Shuhao; Sheu, J.Y.; Ieong, M.; Chiang, Meng-Hsueh; Yamamoto, Tsuyoshi; Liaw, J.J.; Chang, Shun-Bao; Lin, Y.M.; Hsu, Tse-Hsiang; Hwang, Jeong Hyun; Ting, J.K.; Wu, Chih‐Chiang; Ting, Kong; Yang, Fu-Liang; Liu, C.M.; Wu, I-Jhih; Chen, Y.M.; Chent, S.J.; Chen, K.S.; Cheng, Jason; Tsai, Ming-Hsien; Chang, Wei‐Jen; Chen, R.; Chen, C.C.; Lee, T.L.; Lin, Cheng-Chung; Yang, Shu Ching; Sheu, Y-M; Tzeng, J.T.; Lu, Lei; Jang, S. M.; Diaz, C.H.; Mii, YJ

doi:10.1109/cicc.2011.6055355

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Device Scaling Trend and New Tcad Challenges1

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Cited by 9 publications

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“…As illustrated in Figure 1, these innovations include channel mobility enhancement by process-induced strain [4][5][6][7][8][9][10], Tinv scaling with gate tunneling reduction by high-K/metal gate [11][12][13], and electrostatic control improvement by transition from planar single gate to 3D FinFET/Multi-Gate FET (MUGFET) structures [14][15][16][17][18][19][20]. These transistor performance enhancements have also increased process complexity significantly.…”

Section: Device Scaling Trend and New Tcad Challengesmentioning

confidence: 99%