28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-<i>N</i> PLL for 2.4-GHz Internet-of-Things Applications

Gaidioz, David; Cathelin, Andreia; Deval, Yann

doi:10.1109/tmtt.2022.3149826

Cited by 5 publications

(2 citation statements)

References 28 publications

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“…As Table 2 shows, our work has a surface area of 0.1 mm 2 . To give a fair comparison, we have calculated a parameter named Normalized Surface, as [23] has already introduced.…”

Section: Discussionmentioning

confidence: 99%

A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery

et al. 2022

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An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type oscillators. These excellent performances come at the expense of a very poor integration density. To alleviate this issue, this work introduces an injection-locked ring oscillator-based PLL circuit. The combination of the injection-locking process with the use of ring oscillators allows for the benefit of excellent jitter performance while presenting an extremely low surface area due to an architecture without any inductor. The injection locking principle is addressed, and evidence of its phase noise and jitter improvements are confirmed through measurement results. Indeed, phase noise and jitter enhancements up to 43 dB and 23.3 mUI, respectively, were measured. As intended, this work shows the best integration density compared to recent similar state-of-the-art studies. The whole architecture measures 0.1 mm2 while consuming 34.6 mW in a low-cost 180 nm CMOS technology.

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“…As Table 2 shows, our work has a surface area of 0.1 mm 2 . To give a fair comparison, we have calculated a parameter named Normalized Surface, as [23] has already introduced.…”

Section: Discussionmentioning

confidence: 99%

A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery

et al. 2022

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“…This limitation stems from the inherently low phase detection gain in the PFD and the limited switching speed of transistors, especially PMOS devices, utilized in the CP. To address this issue, numerous design alternatives have been proposed in the existing literature [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. A prevalent approach among low-jitter PLL designs in the literature involves using a subsampling structure [1][2][3][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

Tavakoli,

Lavasani,

Sheikhaei

2023

JLPEA

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A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (FoMjitter) ~−236 dB.

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Component-Related Phase Noise Evaluation Method for the LC Oscillators

Bilgehan¹,

Sabuncu²

2023

Circuits Syst Signal Process

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28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

Cited by 5 publications

References 28 publications

A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery

A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

Component-Related Phase Noise Evaluation Method for the LC Oscillators

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