2018 48th European Microwave Conference (EuMC) 2018
DOI: 10.23919/eumc.2018.8541696
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28 GHz 1.8 dB Insertion Loss SPDT Switch with 24 dB Isolation in 65 nm CMOS

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Cited by 18 publications
(2 citation statements)
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“…A DNW transistor is offered in the 0.13 µm CMOS process for better substrate isolation with an additional PN junction 11 . Figure 1D presents the simple structure of DNW, to implement the floating‐body technique, the body is connected to ground through a 5 kΩ resistor, and the DN keeps a high level.…”
Section: Floating‐body Techniquementioning
confidence: 99%
“…A DNW transistor is offered in the 0.13 µm CMOS process for better substrate isolation with an additional PN junction 11 . Figure 1D presents the simple structure of DNW, to implement the floating‐body technique, the body is connected to ground through a 5 kΩ resistor, and the DN keeps a high level.…”
Section: Floating‐body Techniquementioning
confidence: 99%
“…or the combination of series and shunt elements [5], [10]. The multiple cascaded shunt SPDT is usually spaced with quarter wavelength of transmission lines and ideally used for high-power application.…”
mentioning
confidence: 99%