27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

Kim, Yejoong; Jung, Wanyeong; Lee, Inhee; Dong, Qing; Henry, M.; Sylvester, Dennis; Blaauw, David

doi:10.1109/isscc.2014.6757516

Cited by 51 publications

(33 citation statements)

References 5 publications

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“…He has authored or coauthored over 25 Dennis Sylvester received a Ph.D. from the University of California, Berkeley, and is professor of electrical engineering and Computer Science at the University of Michigan, Ann Arbor. He is the director of the Michigan Integrated Circuits Laboratory (MICL), a group of ten faculty and 70+ graduate students.…”

Section: About the Authorsmentioning

confidence: 99%

Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid

Pinckney

Blaauw

Sylvester

2015

IEEE Solid-State Circuits Mag.

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Low-Power Near-Threshold Designnergy-efficient near-threshold design has been proposed to increase energy efficiency across a wide range of applications. This article first provides a background motivating near-threshold and how it differs from super-threshold and subthreshold operation. Next, state-of-the-art near-threshold techniques are summarized that help overcome barriers to near-threshold adoption, namely high variation at low voltage. Last, example industrial and academic wide-voltage scaling systems are discussed.

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Section: About the Authorsmentioning

confidence: 99%

Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid

Pinckney

Blaauw

Sylvester

2015

IEEE Solid-State Circuits Mag.

Self Cite

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“…of the dynamic power in a synchronous system. For this reason, many research works have been performed to develop flip-flops with lower power consumption and better energy efficiency to date [3]- [27].…”

Section: Introductionmentioning

confidence: 99%

A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications

2020

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A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET-FFs can improve energy efficiency by latching input data at both clock edges. When combined with aggressive voltage scaling, significant efficiency improvement is expected. However, prior DET-FF designs were susceptible to Process, Voltage and Temperature (PVT) variations, limiting their operation at low voltage regimes. A fully static truesingle-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold regime. Instead of the two-phase or pulsed clocking scheme in conventional DET-FFs, a True-Single-Phase-Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation. Fully static implementation also enables robust operation in a low voltage regime. The proposed DET-FF is designed in 28nm CMOS technology, and a comprehensive analysis including post-layout Monte Carlo simulation for wide PVT ranges is performed to validate the design approaches. Extensive analysis and comparison with prior-art DET-FFs confirmed that the proposed DET-FF can operate at the lowest voltage of 0.28 V for a temperature range of −40 • C to 120 • C while maintaining nearly-best energy efficiency and power-delay-product. INDEX TERMS Flip-flop, dual-edge-triggered (DET), single phase, low power, near-threshold voltage.

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“…Therefore, reducing flip-flop's power consumption has significant impact on whole system's energy efficiency. Many different types of flip-flops with unique topologies have been studied for achieving better efficiency of flip-flops and processors [3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Lee

2019

IEICE Electron. Express

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A novel static single-phase clocked (SSPC) dual-edge triggered flip-flop (DET-FF) is proposed to allow energy-efficient operation with aggressive voltage scaling. By employing two static latches with a singlephase clock, contention and clock phase mismatch is avoided, which significantly improves tolerance to PVT variations. The post-layout simulation performed with 28 nm CMOS technology shows that the proposed SSPC DET-FF consumes less power and has significantly better powerperformance trade off (PDP) than prior-art DET-FFs. Our Monte Carlo analysis also showed that its supply voltage can be aggressively scaled down to 0.3 V even with PVT variations.

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27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

Cited by 51 publications

References 5 publications

Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid

Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid

A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

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