27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS

Venca, Alessandro; Ghittori, N.; Bosi, Alessandro; Nani, Claudio

doi:10.1109/isscc.2016.7418111

2016 IEEE International Solid-State Circuits Conference (ISSCC) 2016

DOI: 10.1109/isscc.2016.7418111

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27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS

Alessandro Venca¹,

N. Ghittori²,

Alessandro Bosi³

et al.

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27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS

Cited by 1 publication

References 8 publications

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm

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