27‐1: Fabrication Method for Miniaturized CAAC‐OS FET for High‐Definition AR/VR Displays

Abstract

An island formation method for fabrication of a miniaturized CAAC‐OS FET has been developed. With our etching process, the CAAC‐OS FET, which has a gate length as small as 6.5 nm, had a high on‐off drain current ratio. The high‐definition display had excellent characteristics of a low lateral leakage current.

17‐3: An 8.3‐inch 1058‐ppi OLED Display with Side‐by‐Side Pixel Structure Fully Fabricated by Photolithography

“…Furthermore, our technology is also compatible with displays with resolutions of higher than 1000 ppi and larger displays such as TVs, which are difficult to fabricate with a fine metal mask. Utilizing the technology described above, we previously reported the 0.99-inch 2731 ppi OLED display [10] and the 1.5-inch 3207 ppi OLED display [11][12][13][14], each of which uses a silicon substrate and targets applications in VR/AR. The technology can also be employed for a display using a glass substrate.…”

28‐4: 1.50‐Inch, 3207‐ppi OLED Display and Optical System for VR Use

“…However, this coloring method involves light absorption, resulting in low current efficiency and a narrow color gamut. In view of this, we employed the MML technology, in which an OLED layer is patterned by etching in a lithography process [9][10][11]. Through lithography, the MML technology enables patterning for a high aperture ratio, even when the target pixel density is thousands of ppi.…”

Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c-axis aligned crystalline oxide semiconductor FET

“…So far, we have worked on scaling of CAAC-OS FETs by reducing their channel length (L) and channel width (W) sizes and reported the electrical characteristics with a short L. [12][13][14] Meanwhile, the scaling reduces the sizes of source and drain (S/D) electrodes and the diameters of vias connecting the S/D electrodes to wirings and accordingly might increase the resistances of the S/D electrodes and the vias. We therefore examined reducing the sizes of the S/D electrodes and the diameters of the vias connected to wirings in addition to reducing the L/W size of CAAC-OS FETs.…”