25-ns 256K×1/64K×4 CMOS SRAM's

Kayano, S.; Ichinose, K.; Kohno, Y.; Shinohara, Hirofumi; Anami, Keiko; Murakami, Shuji; Wada, T.; Kawai, Y.; Akasaka, Y.

doi:10.1109/jssc.1986.1052596

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Mos Logic and Memory Structure1

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Cited by 13 publications

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“…The power requirement when polysilicon loads are used can be kept very small, an order of magnitude smaller than that for bipolar cells with p n -p load. Recent work has addressed such matters as the improvement of memory speeds, equalization and pre-decoding (Kanyo et al 1986). Two problems remain, namely the limited drive capability of MOS circuits and the low sensitivity of the sense circuit.…”

Section: Mos Logic and Memory Structurementioning

confidence: 99%