25 nm CMOS design considerations

Taur, Yuan; Wann, C.; Frank, D.J.

doi:10.1109/iedm.1998.746474

Cited by 214 publications

(143 citation statements)

References 10 publications

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“…As a result, for a given off-state leakage current specification, the threshold voltage must be raised, thus reducing the on-state drive current. A large channel doping will also inevitably enhance band-to-band tunneling leakage between the body and drain [10]. This will be especially important because abrupt halo doping profiles in the channel are desirable to localize the heavy channel doping whereas abrupt drain doping profiles are desirable for the reduction of series resistance.…”

Section: Circuit Performance Enhancement Of Thin-body Mosfetsmentioning

confidence: 99%

Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

217

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Section: Circuit Performance Enhancement Of Thin-body Mosfetsmentioning

confidence: 99%

Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

217

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“…The reduction of the threshold voltage, however, exponentially increases the subthreshold leakage current [5]. Similarly, a reduction in the gate oxide thickness exponentially increases the mechanical tunneling of the carriers through the oxide, producing significant gate leakage current [6].…”

Section: Introductionmentioning

confidence: 99%

Path Specific Register Design to Reduce Standby Power Consumption

Salman

2011

JLPEA

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A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current.

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“…This has implied further reduction of contact dimensions, which now reaches diameters of less than 50 nm [4,5]. These "nano vias" are of the utmost importance to get the best performance of the FF, mainly because of series resistance and parasitic capacitance considerations.…”

Section: Introductionmentioning

confidence: 99%

“…These "nano vias" are of the utmost importance to get the best performance of the FF, mainly because of series resistance and parasitic capacitance considerations. Recently, during several failure tests, it has been observed that copper nano vias are literally destroyed (Figure 1) under high fluence stress [1][2][3][4][5][6]. This may find an explanation by localized heating due to Joule effect, but first order calculations based on simplified thermal considerations show rather low temperature in order to explain void presence in the nano vias, which such be over, at least, copper silicate formation temperature (823 K) [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia

Oviedo

Trojman

Kauerauf

et al. 2013

Av. Cienc. Ing. (Quito)

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This paper presents the development of a thermal-electrical finite element (FE) model with the objective to analyze failure mechanisms responsible of physical degradation (void, copper silicate formation, etc.) caused by high fluence stress of 90nm copper vias for FinfET devices. Indeed in [1], this physical degradation was interpreted as a main consequence of Joule effect, however their employed model reached too low temperatures to explain the observed physical degradation. In order to confirm this, the steady-state FE model developed in this work computes the temperature increase and distribution caused by high electrical current density flowing through a copper contact, considering non-ideal thermal and electrical interfaces. In addition, a sensitivity analysis is performed as a way to identify critical failure parameters. The temperature response of the model to independent variation of electrical resistivity of studied materials, and interfacial electrical and thermal conductance between the copper contact and its diffusion barrier were obtained. The decrease of interfacial electrical conductance triggers steady-state temperatures over copper and silicate melting points and, in consequence leads to temperature high enough to explain the physical degradation.Keywords. copper nano vias, Joule heating, finite element analysis, interface electric conductivity, sensitivity analysis. ResumenEste trabajo presenta el desarrollo de un modelo termo-eléctrico de elementos finitos (EF) con el fin de analizar los mecanismos de falla responsables de la degradación física causada por alta densidad de corriente en contactos de cobre de 90 nm empleados en dispositivos FinFET. De hecho en [1], esta degradación física fue interpretada como consecuencia principal del efecto Joule, sin embargo el modelo empleado alcanzó temperaturas demasiado bajas comparadas con el daño observado. Con el propósito de confirmar esta hipótesis, el modelo de EF de estado estable desarrollado en este trabajo calcula el incremento y la distribución de temperatura causada por alta densidad de corriente eléctrica fluyendo a través de un contacto de cobre, tomando en cuenta interfaces eléctricas y térmicas no idealizadas. Además, un análisis de sensibilidad fue realizado como un medio para identificar parámetros críticos de falla. La respuesta del modelo ante la variación independiente de la resistividad eléctrica de los materiales estudiados, y las conductancias eléctricas y tér-micas entre el contacto de cobre y su barrera de difusión fue obtenida. La disminución de la conductancia eléctrica de dicha interfaz desencadenó temperaturas de estado estable superiores a los puntos de fusión del cobre y los silicatos del contacto y, en consecuencia, permite explicar la degradación física observada.Palabras Clave. nano contactos de cobre, calentamiento Joule, análisis de elementos finitos, conductividad eléctrica de interfaz, análisis de sensibilidad.

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25 nm CMOS design considerations

Cited by 214 publications

References 10 publications

Extremely scaled silicon nano-CMOS devices

Extremely scaled silicon nano-CMOS devices

Path Specific Register Design to Reduce Standby Power Consumption

Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia

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