24-channel 32 kb/s ADPCM transcoder using the CCITT recommendation G.721

Abstract

The 32 kb/s ADPCI4 staidard algorithm has been published in the CCITT recommendation G.72l. Implementationsfor this algorithm have been proposed in the form of a per-channel transcoder. This paper presents an alternative implementation which is preferred for multi-channel applications. It uses a combination of CMOS EPROM lookup table and CMOS gate array processor technologies. The paper presents the transcoder architecture which is based on a multiprocessor concept.The hardware block diagram and the firmware structure •are discussed. System design and test results were obtained using a hardware prototype in which the functions of the CMOS gate array were temporarily implemented by ALS/Fast standard discrete logic components.