24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing

Yamaoka, Masanao; Yoshimura, Chihiro; Hayashi, Masato; Okuyama, Toru; Aoki, Hidetaka; Mizuno, Hiroyuki

doi:10.1109/isscc.2015.7063111

Cited by 135 publications

(109 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Ising chip is extended by the spin unit, which is connected to 5 nearest-neighbor spin units and forms a 2-layer 2-dimensional lattice [2]. A spin unit has a memory cell array to represent a spin and coefficients, and the decision circuit that determines the next state of the spin.…”

Section: Proposed Designmentioning

confidence: 99%

“…Generally, finding the global optimum solution to them in conventional computer needs exponential time. CMOS implementation of Ising computing has been proposed previously to solve this problem with its own convergence property [2]. It maps the problem to the coefficients of Ising model firstly and then activates the ground-state search by interaction between spins.…”

Section: Introductionmentioning

confidence: 99%

“…A lot of randomization methods have been proposed to help the system to escape from the local optimum. Such as using highly amplified Gaussian thermal noise [7], using additional linear feedback shift register to generate a pseudorandom bit stream [8], using optoelectronic CMOS circuit [9], using external random number [2]. All the methods above need extra hardware cost to intentionally induce randomness, which will add the cost of VLSI implementation.…”

Section: Introductionmentioning

confidence: 99%

“…All the methods above need extra hardware cost to intentionally induce randomness, which will add the cost of VLSI implementation. A method utilizing the intrinsic noise of integrated circuit is proposed by Hitachi [2] to induce randomness without any extra hardware. It destroys the memory cells randomly by reading them under low supply voltage.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Novel Structure to Realize Memory Cell Fluctuation Under Voltage Control in Ising Chip

Wang¹,

Chen²,

Zhang³

2017

Proceedings of the International Conference on Computer Networks and Communication Technology (CNCT 2016)

View full text Add to dashboard Cite

Abstract. New computing architecture utilizing the noise of integrated circuit to realize indeterminate computing has been proposed previously to solve combinatorial optimization problems. But the solution accuracy of realizing indeterminate computing with circuit's noise performed significantly worse than that with external random number. Because large scale of time is spent to introduce randomness in reading memory cells by row, which reduces the effective computing time. This paper presents a novel structure to introduce probabilistic behavior with just one read operation. It improves the rate of effective computing time and can get close solution accuracy to the scheme using external random number but with less cost.

show abstract

Section: Proposed Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Novel Structure to Realize Memory Cell Fluctuation Under Voltage Control in Ising Chip

Wang¹,

Chen²,

Zhang³

2017

Proceedings of the International Conference on Computer Networks and Communication Technology (CNCT 2016)

View full text Add to dashboard Cite

show abstract

“…Some architectures rely on emerging devices such as superconductors to enable the quantum superposition [8], while others are still based on silicon integrated circuits [3,12]. We previously proposed an SRAM-based integrated circuit to perform a lower-energy-state search of the Ising model [7,[18][19][20][21]. Our architecture aims to solve combinatorial optimization problems to operate social infrastructure efficiently.…”

Section: Introductionmentioning

confidence: 99%

Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing

Yoshimura

Hayashi

Okuyama

et al. 2017

IJNC

Self Cite

View full text Add to dashboard Cite

The non-von Neumann computer architecture has been widely studied to prepare us for the post-Moore era. The authors implemented this kind of architecture, which finds the lower energy state of the Ising model using circuit operations inspired by simulated annealing in SRAM-based integrated circuits. Our previous prototype was suited for the Ising model because of its simple and typical structure such as its three-dimensional lattice topology, but it could not be used in real world applications. A reconfigurable prototyping environment is needed to develop the architecture and to make it suitable for applications.Here, we describe an FPGA-based prototyping environment to develop the annealing processor's architecture for the Ising model. We implemented the new architecture using a prototyping environment. The new architecture performs approximated simulated annealing for the Ising model, and it supports a highly complex topology. It consists of units having fully-connected multiple spins. Multiple units are placed in a two-dimensional lattice topology, and neighboring units are connected to perform interactions between spins. The number of logic elements was reduced by sharing the operator among multiple spins within the unit. Furthermore, a pseudorandom number generator, which produces random pulse sequences for annealing, is also shared among all the units. As a result, the number of logic elements was reduced to less than 1/10, and the solution accuracy became comparable to that of a conventional computer's simulated annealing.

show abstract

Quantum Analog Annealing of Gain‐Dissipative Ising Machine Driven by Colored Gaussian Noise

Liao

Sarker

et al. 2022

Advcd Theory and Sims

View full text Add to dashboard Cite

Gain‐dissipative Ising machines (GIMs) are a type of quantum analog equipment that can rapidly determine the optimal solution for combinatorial optimization problems. When the noise intensity is significantly lower than the fixed point of the system, the performance of a GIM is not influenced by the fluctuation of the noise intensity. However, the noise in this study is limited to Gaussian white noise. The influence of prevalent colored noise on GIMs has not been researched. In this study, the influence of common‐colored noise on the performance of GIMs is numerically investigated. The results of a domain clustering dynamics analysis reveal that red noise can better suppress the generation of the noise‐induced irregular temporary domain. Furthermore, several prevalent MAXCUT problem topologies, including the Moebius ladder, random Moebius ladder, and 2D random lattice, are adopted as test benchmarks. The results reveal that GIMs influenced by white, blue, and violet noise perform better at low‐intensity noise condition. In contrast, pink and red noise‐injected GIMs demonstrate higher performances when applied to MAXCUT topologies with both ferromagnetic and antiferromagnetic connections under larger noise intensity conditions. This indicates that the noise dispersion can be used as an additional hyperparameter to optimize the performance of GIMs.

show abstract

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing

Cited by 135 publications

References 3 publications

A Novel Structure to Realize Memory Cell Fluctuation Under Voltage Control in Ising Chip

A Novel Structure to Realize Memory Cell Fluctuation Under Voltage Control in Ising Chip

Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing

Quantum Analog Annealing of Gain‐Dissipative Ising Machine Driven by Colored Gaussian Noise

Contact Info

Product

Resources

About