22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

Oh, Chisung; Chun, Ki Chul; Byun, Young-Yong; Kim, Yong-Ki; Kim, Soyoung; Ryu, Yesin; Park, Jaewon; Kim, Sinho; Cha, Seung-Do; Shin, Dong‐Hui; Lee, Jungyu; Son, Jaeman; Ho, Byung-Kyu; Cho, Seong-Jin; Kil, Beomyong; Ahn, Sungoh; Lim, Bianca; Park, Yong-Sik; Lee, Ki-Jun; Lee, Myung-Kyu; Baek, Seungduk; Noh, Junyong; Lee, Jae‐Wook; Lee, Seungseob; Kim, Soo‐Young; Lim, Bo-Tak; Choi, Seouk-Kyu; Kim, Jin-Guk; Choi, Hye-In; Kwon, Hyuk‐Jun; Kong, Jun Jin; Sohn, Kiwon; Kim, Nam Sung; Park, Kwang-Il; Lee, Jung-Bae

doi:10.1109/isscc19947.2020.9063110

Cited by 36 publications

(9 citation statements)

References 2 publications

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“…TSVs with micro-bumps are conventionally used for the high-bandwidth memory (HBM) [82][83][84][85][86][87], as shown in Figure 29. However, there are several issues when using micro-bumps.…”

Section: Bbcube Drammentioning

confidence: 99%

“…In the case of the KGD process on the other hand, the dies were disposed of, which was in vain [101]. The TSV area connected neighboring banks to other layers, to avoid longer intra-die wiring [85][86][87]. The neighboring banks associated with the same TSV "digits" were grouped into bank groups, which corresponded to tiles in the case of BBCube.…”

Section: Layer Addition To Cover Circuit Resourcesmentioning

confidence: 99%

“…This 2D redundancy was carried out on a die-by-die basis within each layer of the stack. Recent DRAM devices were provided with extra cell arrays occupying 10% to 20% of the total area to reduce bit error rate (BER), in both cases of block sparing type redundancy and error check and correction (ECC) [86]. In this paper, we used a simple sub-array sparing model to be discussed later, to evaluate the area overhead.…”

Section: Introduction To 3d Redundancymentioning

confidence: 99%

“…Figure29. HBM road map with micro-bumps, where HBM[82], HBM2[83][84][85], HBM2E[86,87], respectively.…”

mentioning

confidence: 99%

“…Figure34. A comparison of the data bandwidth and TSV I/O power consumption between HBM and BBCube, where HBM2[85], HBM2E[86], repectively.…”

mentioning

confidence: 99%

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Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

et al. 2022

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Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

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