20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

Yamada, Hitoshi; Tsunotani, Masanori; Kaneyama, F.; Seki, S.

doi:10.1109/4.553175

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…The maximum switching capacity reported to date for LSI-based ATM switching systems is 160 Gbit/s [2]. One limitation for expanding this switching capacity into Tbit/s order is the memory access speed of the semiconductor memory devices used in cell-buffer storage [3,4]. Although the shift register is the fastest device in conventional semiconductor memory devices, the maximum clock frequency reported to date is no more than 3 GHz [4].…”

Section: Introductionmentioning

confidence: 99%

“…One limitation for expanding this switching capacity into Tbit/s order is the memory access speed of the semiconductor memory devices used in cell-buffer storage [3,4]. Although the shift register is the fastest device in conventional semiconductor memory devices, the maximum clock frequency reported to date is no more than 3 GHz [4]. This is because the propagation delay time between the registers occupies a large part of the cycle time.…”

Section: Introductionmentioning

confidence: 99%

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Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Tahara¹

1999

Supercond. Sci. Technol.

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We have developed a 10 GHz 32-bit delay-line memory, using a semiconductor crossbar switch and a YBa2Cu3O7- coplanar delay line. For use in the high-speed (10 GHz) cell-buffer storage of large-throughput (1 Tbit/s) asynchronous transfer mode (ATM) switching systems, this memory must be fairly reliable. To evaluate the reliability of the operation, therefore, we measured the clock-frequency and temperature margins and the temperature dependence of the bit-error rate. At 64 K, this memory has a capacity of 32 bits with a clock frequency of 9.89±0.11 GHz. In general, clock frequencies of communication systems are strictly managed so that the margins are less than 10-6. Therefore, the frequency margin of this memory (~2 × 10-2) is wide enough for use in communication systems. The temperature margin was 71.5±4.3 K at 10 GHz and 33 bits. This memory offered error-free operation (BER < 10-13) at 71.5±3.5 K. These temperature margins are wide enough to be controlled by a cryocooler. These results show that the memory offers reliability and that it can be applied to high-speed ATM cell-buffer storage.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Tahara¹

1999

Supercond. Sci. Technol.

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“…The direct-coupled field-effect transistor logic ͑DCFL͒ digital devices with a GaAs transistor are suitable because of its high integration, high switching speed, and low power dissipation capability. [1][2][3][4][5] In addition, the enhancement transistor is used as the driver transistor and the depletion transistor is used as the load transistor in the conventional DCFL. Although conventional enhancement/depletion ͑E/D͒ logic has large noise margin, high speed, and low power dissipation, it also has some disadvantages, such as complicated structure, difficult fabrication process, and low yield.…”

mentioning

confidence: 99%

Self-Aligned Enhancement-Mode and Parasite Depletion-Mode Heterojunction Doped-Channel FET for Low Power Supply DCFL Application

Tan¹,

Liao²

2007

J. Electrochem. Soc.

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We demonstrate that a heterojunction doped-channel field-effect transistor ͑HDCFET͒ structure, using an additional p + -GaAs cap layer, simultaneously obtains both p-n junction and Schottky junction to fabricate the enhancement mode and depletion mode of HDCFET ͑EHDCFET and DHDCFET͒ on the same chip, thus implementing a direct-coupled field effect transistor logic ͑DCFL͒ circuit. In addition, an additional p + -GaAs cap layer can perform controllable undercut profile with wet etching to proceed with self-aligned technology resulting in a T-shaped gate structure. The microwave characteristics have also been investigated. The cutoff frequency of the E/D inverter ͑EDI͒ is nearly the same with the self-aligned EHDCFET for varied gate-source voltage. When V GS = 0.7 V, the cutoff frequency for three self-aligned EHDCFET, parasitic DHDCFET, and EDI are 16.8 GHz, 9.8 GHz, and 17 GHz, respectively. The self-aligned EHDCFET dominates the EDI electrical performances. Furthermore, the better inverter performances, the logic-low noise margin and logic-high noise margin, are found to be 260 mV and 360 mV, respectively.The gallium arsenide ͑GaAs͒ transistor has obvious advantages over the silicon ͑Si͒ transistor in performances of speed, power, and rf frequencies. With increasing the channel of wavelength division multiplexing ͑WDM͒ and over 10 Gb/s operation in optical communication system, higher integration and lower power dissipation are necessary. To achieve such performances, GaAs logics have been proposed as an alternative to Si logic to reduce the power dissipation and improve speed. The direct-coupled field-effect transistor logic ͑DCFL͒ digital devices with a GaAs transistor are suitable because of its high integration, high switching speed, and low power dissipation capability. [1][2][3][4][5] In addition, the enhancement transistor is used as the driver transistor and the depletion transistor is used as the load transistor in the conventional DCFL. Although conventional enhancement/depletion ͑E/D͒ logic has large noise margin, high speed, and low power dissipation, it also has some disadvantages, such as complicated structure, difficult fabrication process, and low yield. In E/D logic circuit, it requires one to control the threshold voltages of enhancement transistor and depletion transistor precisely on the same wafer. Because physical properties of GaAs are different from those of Si, ion implementation is harder to control in GaAs than in Si. Material nonuniformities cause nonuniform transistor characteristics that cause threshold voltage variation across a wafer and from wafer to wafer. This results in increased processing complexity. In order to improve the performance and processing complexity of conventional E/D logic, we first demonstrate the facility of direct-coupled FET logic circuit made with the same epitaxial structure simultaneously of self-aligned E-and parasitic D-mode heterojunction doped-channel field-effect transistors ͑HD-CFETs͒ on the same chip. The key feature of the proposed device structur...

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A Superconducting Delay-Line Memory Using a YBa2Cu3O7-δ Coplanar Line

Yoshitake

Tahara

1999

Advances in Superconductivity XI

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20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

Cited by 6 publications

References 9 publications

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Clock-frequency and temperature margins of a high-temperature superconductor delay-line memory

Self-Aligned Enhancement-Mode and Parasite Depletion-Mode Heterojunction Doped-Channel FET for Low Power Supply DCFL Application

A Superconducting Delay-Line Memory Using a YBa2Cu3O7-δ Coplanar Line

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