2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Yamauchi, Tsuyoshi; Yamada, H.; Nishiyama, Tomoki; Shimamura, K.; Tanaka, Satoshi; Hotta, Takashi; Shimizu, T.; Sawamoto, H.

doi:10.1109/4.508211

Cited by 18 publications

(9 citation statements)

References 9 publications

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“…The combined behavior of their stages, from the input of the first to the output of the second or third gate, are subject to the principles of our analysis. Similarly the H/L and L/H gate types from the CDPD technique [6], and the NTP circuits [11] are not directly analyzed because both families are optimized versions of Domino Logic gates. A technique which is fully covered here.…”

Section: A Fundamental Gate-design Methodsmentioning

confidence: 99%

Compatible cell connections for multifamily dynamic logic gates

Ortiz

Knight

2002

IEEE Trans. VLSI Syst.

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Dynamic Logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections are then identified and later applied to discover which are the feasible connections between cell circuit types identified.Index Terms-Dynamic logic, logic circuits, single-phase-clock (SPC), true-single-phase-clock (TSPC).

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Section: A Fundamental Gate-design Methodsmentioning

confidence: 99%

Compatible cell connections for multifamily dynamic logic gates

Ortiz

Knight

2002

IEEE Trans. VLSI Syst.

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“…Murabayashi [2] found that NTP was 9-21% faster than a conventional feedback keeper for the same noise immunity. However, it was unclear if the gates had the same input capacitance.…”

Section: Discussionmentioning

confidence: 99%

“…A number of authors have proposed replacing the keeper with a weak complementary pMOS network shown in Figure 1(b). The technique has been variously called Noise Tolerant Precharge (NTP) [1], [2] or Monotonic CMOS [3]. Skewed CMOS [4] is a closely related technique alternating one NTP stage for every two skewed static CMOS stages.…”

Section: Introductionmentioning

confidence: 99%

Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic

Harris

Breed

Erler

et al. 2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03

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Dynamic logic requires some sort of keeper to prevent the output node from floating and to provide acceptable noise immunity. A number of recent papers have advocated using a very weak complementary pMOS network in place of the conventional feedback keeper; such a technique is called Noise-Tolerant Precharge (NTP). This paper compares the delay and noise margin of NTP with conventional feedback keepers. Although NTP is more robust in that it can recover from a dynamic noise event, it is also 5-50% slower than conventional feedback keepers with the same static noise margin.

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“…One of domino drawbacks is the inability to recover after noise upsets. Noisetolerant precharge solves this problem at the price of increased gate capacitance [2]. Another major disadvantage of domino logic is the increased clock loading and the need to deliver the clock signal to every gate, which in turn increases power, routing area and design complexity.…”

Section: Introductionmentioning

confidence: 99%

Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family

Akl

Bayoumi

2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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We present a new dynamic-like static circuit family called Feedback-Switch Logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of Cascode Voltage Switch Logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking.

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2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Cited by 18 publications

References 9 publications

Compatible cell connections for multifamily dynamic logic gates

Compatible cell connections for multifamily dynamic logic gates

Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic

Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family

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