2.2 GHz All-n-p-n Second-Generation Controlled Conveyor in Pseudoclass AB Using 0.8-&amp;lt;tex&amp;gt;$mu$&amp;lt;/tex&amp;gt;m BiCMOS Technology

“…TIAs and current conveyors exceeding the 2 GHz bandwidth have been fabricated in BiCMOS processes [41][42][43]. In dedicated optical telecommunication processes, ultra wideband TIAs above 10 GHz are common showing that using specific, hybrid or 3D technologies the ISC performances reported in this paper could be increased by a factor of 10.…”

Section: Discussionmentioning

confidence: 88%

Streak camera in standard (Bi)CMOS (bipolar complementary metal-oxide-semiconductor) technology

Zlatanski¹,

Uhring²,

Normand³

et al. 2010

Meas. Sci. Technol.

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The conventional streak camera (CSC) is an optoelectronic instrument that captures the spatial distribution as a function of time of an ultra high-speed luminous phenomenon with picosecond temporal resolution and a typical spatial resolution of several tens of micrometers. This paper presents two tubeless streak camera architectures called MISC (matrix integrated streak camera) and VISC (vector integrated streak camera), which replicate the functionality of a CSC on a single CMOS chip. The MISC structure consists of a lens, which spreads the photon flux on the surface of a specific pixel array-based (Bi)CMOS sensor. The VISC architecture is based on a sensor featuring a single column of photodetectors, where each element is coupled to a front-end and a multi-sampling and storage unit. In this case the optical objective used in front of the sensor focuses the luminous event on the several tens of micrometers wide photosensitive column. For both architectures, the spatial resolution is linked to the size of the photodetector and the temporal resolution is determined by the bandwidths of the photodetectors and the signal conditioning electronics. The capture of a 6 ns full width at half maximum 532 nm laser pulse is reported for two generations of MISC and a first generation of VISC.

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“…4. This is very similar to the architecture shown in [15] except that the output stage is cascoded using Q2. This allows operation of the circuit to be extended close to 6GHz.…”

Section: B Impedence Inverter Blockmentioning

confidence: 95%

“…The voltage at terminal X is followed by terminal Y and the current in terminal X is conveyed to terminal Z. The details of how the connection of the two CCII-forms an impedance inverter is shown in [15]. The circuit diagram for each CCII-is shown in Fig.…”

Section: B Impedence Inverter Blockmentioning

confidence: 99%

A design technique for concurrent multiband tunable loads from 0.4–6GHz with independent Q tuning

Gamlath

Arabi

Morris

et al. 2017

2017 IEEE Asia Pacific Microwave Conference (APMC)

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This paper presents a preliminary attempt at designing a concurrent multiband tunable load. Each band is independently tunable and the centre frequency of each band can be placed anywhere from 400MHz to 6GHz. This is done through the use of high frequency impedance inverters which enable each band to be tuned independently. The design has been implemented in a low cost 0.25µm BiCMOS process using 1µm HBTs operating at 1.2mA from a +/-2.2V supply. The circuit is targeted at 5G wideband applications requiring narrow band filtering where the bandwidth also needs some degree of tunability. The results show that high Q factors of over 100 can be achieved and that the individual bands show independent tunability. Although the circuit is demonstrated for three bands it is easily extendible to a higher number of bands.

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2.2 GHz All-n-p-n Second-Generation Controlled Conveyor in Pseudoclass AB Using 0.8-<tex>$mu$</tex>m BiCMOS Technology

Cited by 19 publications

References 8 publications

CMOS CCCII: Structures, characteristics, and considerations

CMOS CCCII: Structures, characteristics, and considerations

Streak camera in standard (Bi)CMOS (bipolar complementary metal-oxide-semiconductor) technology

A design technique for concurrent multiband tunable loads from 0.4–6GHz with independent Q tuning

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