1S-1R array: Pure-memristor circuit for binary neural networks

Zhang, Zhang; Ge, Zhiheng; Wei, Yadong; Cheng, Xin; Xie, Guangjun; Liu, Gang

doi:10.1016/j.mee.2021.111697

Cited by 3 publications

(2 citation statements)

References 16 publications

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“…Also, V. Parmar et al [154] presented stochastic sampling CIM based on OxRAM circuit. In [155], the authors utilized a 1-selector 1-resistor architecture instead of a 1-transistor 1-resistor array of the memristor structure to obtain high speed, and high-density integration. While in [156], the authors used a 3D-memristor structure for low power consumption.…”

Section: A: Computing In Memorymentioning

confidence: 99%

A Systematic Literature Review on Binary Neural Networks

et al. 2023

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This paper presents an extensive literature review on Binary Neural Network (BNN). BNN utilizes binary weights and activation function parameters to substitute the full-precision values. In digital implementations, BNN replaces the complex calculations of Convolutional Neural Networks (CNNs) with simple bitwise operations. BNN optimizes large computation and memory storage requirements, which leads to less area and power consumption compared to full-precision models. Although there are many advantages of BNN, the binarization process has a significant impact on the performance and accuracy of the generated models. To reflect the state-of-the-art in BNN and explore how to develop and improve BNNbased models, we conduct a systematic literature review on BNN with data extracted from 239 research studies. Our review discusses various BNN architectures and the optimization approaches developed to improve their performance. There are three main research directions in BNN: accuracy optimization, compression optimization, and acceleration optimization. The accuracy optimization approaches include quantization error reduction, special regularization, gradient error minimization, and network structure. The compression optimization approaches combine fractional BNN and pruning. The acceleration optimization approaches comprise computing in-memory, FPGA-based implementations, and ASIC-based implementations. At the end of our review, we present a comprehensive analysis of BNN applications and their evaluation metrics. Also, we shed some light on the most common BNN challenges and the future research trends of BNN.

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Section: A: Computing In Memorymentioning

confidence: 99%

A Systematic Literature Review on Binary Neural Networks

et al. 2023

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“…Nevertheless, in certain circuits that substitute memristors for MOS transistors, the property of the resistance value changing with voltage restricts the usage of memristors and occasionally necessitates the inclusion of extra peripheral circuitry to guarantee the correct execution of the function. This, however, makes the circuit design more complicated and negates the goal of employing memristors to achieve a higher level of integration.Conventional two-terminal memristors are vulnerable to interference from external magnetic fields in industrial generation, and a change in resistance value would impact the performance of the circuit stability[10]. A three-terminal memristor model is suggested to accomplish anti-interference protection for stored data in order to strengthen the stability of the memristor and protect it from outside interference when data input to it happens and when data storage is to be done.Compared to two-terminal memristors, three-terminal memristors have the following performance and application advantages by adding a port to control the shielding from external electromagnetic interference:…”

mentioning

confidence: 99%

Modeling and circuit design for three-terminal memristors

Kuang,

huan,

xiao

2023

Preprint

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In this paper, a three-terminal memristor model is developed in order to improve the anti-interference performance of the memristor and address the issue that the resistance value of the conventional two-terminal memristor is readily impacted by voltage. In order to simulate and validate the function of the three-terminal memristor, the logic circuit and multiplication circuit are developed using this model in this work using the cadence ic617 program. According to the findings, the three-terminal memristor multiplication circuit uses less energy than the typical conventional multiplier circuit, consuming only 0.335 uW. The memristor offers the benefits of low power consumption, compact size, and great integratability as a nanoscale device. The use of three-terminal memristors can dramatically reduce the number of chip components and improve chip integration when Moore's law approaches a limit.

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