In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to achieve better lock time and jitter performance. This work derives stability conditions for such DPLL architectures using Multiple Lyapunov Functions (MLFs) for switched systems. The loop-parameters chosen on the basis of these stability conditions ensure that chattering phenomenon does not occur during switching between different subsystems. A 5 GHz fractional-N DPLL designed with these loop-parameter values is fabricated in CMOS65 nm-LL technology. The measured settling time of the implemented DPLL is within 1 µs. The efficiency of switching rule and stability conditions used for this DPLL is validated with the fast settling response, which is the best lock time reported until now for fractional-N DPLLs.