19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC

Ahmad, Fazil; Unruh, Greg; Iyer, Amrutha; Su, Pin-En; Abdalla, Sherif; Shen, Bo; Chambers, Mark; Fujimori, Ichiro

doi:10.1109/isscc.2016.7418038

Cited by 3 publications

(1 citation statement)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In PLLs employing LC oscillators, a trade-off between settling time and output jitter exists based on the loop bandwidth. For reducing both lock-time and jitter simultaneously, the concept of adaptive loop gain has been widely used in digital phase-locked loop (DPLL) architectures [1], [2], [3], [4]. Few DPLL designs also employ switching between linear and non-linear phase detection mechanism, to reduce high-resolution requirement on succeeding Time-to-Digital Converter (TDC) block.…”

Section: Introductionmentioning

confidence: 99%

Stability Analysis for Fast Settling Switched DPLL

Paliwal¹,

Pal²,

Gupta³

2018

Preprint

View full text Add to dashboard Cite

In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to achieve better lock time and jitter performance. This work derives stability conditions for such DPLL architectures using Multiple Lyapunov Functions (MLFs) for switched systems. The loop-parameters chosen on the basis of these stability conditions ensure that chattering phenomenon does not occur during switching between different subsystems. A 5 GHz fractional-N DPLL designed with these loop-parameter values is fabricated in CMOS65 nm-LL technology. The measured settling time of the implemented DPLL is within 1 µs. The efficiency of switching rule and stability conditions used for this DPLL is validated with the fast settling response, which is the best lock time reported until now for fractional-N DPLLs.

show abstract