16-60 V rated LDMOS show advanced performance in a 0.72 μm evolution BiCMOS power technology

Tsai, Chin-Yu; Efland, T.; Pendharkar, S.; Mitros, J.; Tessmer, A.J.; Smith, J.; Erdeljac, J.; Hutter, Lou N.

doi:10.1109/iedm.1997.650401

Cited by 26 publications

(3 citation statements)

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“…In addition, for cost and reliability reasons, there is a continuous trend for integrating these transistors in the low voltage CMOS process instead of using discrete devices. Hence the so-called ''smart power technologies": technologies with a deep submicron core, embedded memory, and integrated power devices [5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

Moens

bosch

2008

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

Moens

bosch

2008

Microelectronics Reliability

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“…It is known that the laterally diffused metal oxide semiconductor (LDMOS) is becoming increasingly important in high-power and high-voltage applications. 1) Figures 1(a) and 1(b) compare cross-sections of a typical n-type structure LDMOS and the reduced surface field (RESURF) LDMOS. 2) As can be seen, a specific feature of the RESURF LDMOS is the shallow lightly doped n-type drift region fabricated on the p-type Si substrate.…”

Section: Introductionmentioning

confidence: 99%

Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics

Saito

Tanaka

Hayashi

et al. 2011

Jpn. J. Appl. Phys.

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In this paper, an accurate model of resistive drift region in laterally diffused metal oxide semiconductor (LDMOS) is presented. We have improved the dynamically varying depletion width model at the drift/substrate junction, by considering both the drain and substrate bias effects. The both bias condition causes the resistance modification of the high resistive drift region for the reduced-surface-field structure (RESURF). In addition, new expansion-effect model is developed by considering the substrate bias effect. The developed models have been implemented into Hiroshima University starc insulated gate field effect transistor model for high voltage (HiSIM-HV) and it is proved that the models reproduce measured direct current (DC) characteristics for the wide variety of the substrate bias variation.

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“…1. 1) It has been observed that the capacitance of the LDMOS devices show often anomalous characteristics as a function of applied voltage. This is modeled either by introducing an internal node at the channel/drift junction 2,3) or a resistance as a macro model.…”

Section: Introductionmentioning

confidence: 99%

Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization

Yokomichi

Sadachika

Miyake

et al. 2008

jjap

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A laterally diffused metal oxide semiconductor (LDMOS) device enables the realization of a wide range of application voltages by varying impurity concentration and the length of the lightly doped drain contact region. However, this resistive contact region causes the abnormal characteristics observed in capacitances. Here, the HiSIM-LDMOS model based on a complete surface-potential description is demonstrated, which simulates the features of the LDMOS device consistently. With this model, an optimization scheme for the LDMOS device for requested features is discussed.

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16-60 V rated LDMOS show advanced performance in a 0.72 μm evolution BiCMOS power technology

Cited by 26 publications

References 1 publication

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics

Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization

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