15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Si, Xin; Tu, Yung-Ning; Huanq, Wei-Hsing; Su, Jian‐Wei; Lu, Pei-Jung; Wang, Jinghong; Liu, Chun‐Jen; Wu, Shaoen; Liu, Ruhui; Chou, Yen-Chi; Zhang, Zhixiao; Sie, Syuan-Hao; Wei, Weichen; Lo, Yun-Chen; Wen, Tai-Hsing; Hsu, Tzu-Hsiang; Chen, Yen-Kai; Shih, William M.; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Lien, Nan-Chun; Shih, Wei-Chiang; He, Yajuan; Li, Qiang; Chang, Meng‐Fan

doi:10.1109/isscc19947.2020.9062995

Cited by 140 publications

(36 citation statements)

References 2 publications

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“…The classification accuracy is close to the digital implementations and may much better than prior in-memory approaches [18]. After that, many high precision SRAM-based in-memory approaches have been proposed to accelerate neural networks beyond the MNIST and LeNet-5 convolutional neural network (CNN) [19]- [21]. In addition, the circulant matricesbased CNN was proposed to overcome limitations induced by the irregular network structure.…”

Section: B the Memory-centric And Transpose-based Nn Acceleratormentioning

confidence: 85%

Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor

Chang

Zhu

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Emerging energy-efficient neural network processor is a promising hardware design to accelerate neural network algorithms with high performance and low power consumption. Typically, static random-access memory (SRAM) is employed to develop large buffers using in the processor. The bit cell of SRAM contains six transistors, leading to low density and large leakage current. In particular, several AI processors need multiple port and transfer-based SRAMs, which decrease the density and increase the power consumption. Recently, emerging spin-orbit torque magnetic random-access memory (SOT-MRAM) becomes a possible solution to replace the SRAM as working memory. However, more operations should be supported by the SOT-MRAM to provide sufficient functions, such as multiple-port memory, transpose memory, data-streaming operations. In this paper, we develop the working memory of neural network processor with SOT-MRAM to build the design library including the transpose operations, multiple-port memory, and data-streaming based buffer arrays. Equiped with those operations provided by SOT-MRAM, we can build high performance and energy-efficient neural network processors.

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Section: B the Memory-centric And Transpose-based Nn Acceleratormentioning

confidence: 85%

Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor

Chang

Zhu

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Therefore, enabling dedicated security is paramount of importance in future wearable systems [4,25]. While the problems of security and privacy [11,55], power and computational efficiency [22,30,44] in Edge AI have already been of interest in recent studies, research in this area is ongoing.…”

Section: Related Challengesmentioning

confidence: 99%

When wearable technology meets computing in future networks

Ometov

Chukhno

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

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Rapid technology advancement, economic growth, and industrialization have paved the way for developing a new niche of small body-worn personal devices, gathered together under a wearabletechnology title. The triggers stimulated by end-users interest have introduced the first generation of mass-consumer wearables in just the past decade. Evidently, the trailblazing ones were not designed with strict energy-consumption restrictions in mind. Thus, wearable-computing-related research remained fragmented. Advanced and sophisticated batteries and communication technologies could be already procurable on devices. Additional solutions for efficient utilization of processing power are still a white spot on the wearable technology roadmap. A-WEAR EU project aims to enhance the understanding of how the superimposition of those technologies would improve wearable devices' energy efficiency, with the research area being far from saturation. We foresee enormous room for research as the Edge computing paradigm is emerging towards hand-held devices. CCS CONCEPTS• General and reference → Cross-computing tools and techniques; • Hardware → Networking hardware; Wireless devices; Emerging architectures; • Computer systems organization → Distributed architectures; • Networks → Network topology types; Wireless access networks.

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“…Then, the quantified digital results are put into the shifter and adder so as to generate the final result. The feasibility of VIVO based on 6T SRAM has been validated in [2], and works on dualsplit 6T [3] and 12T [4] are also presented. One concern for VIVO architecture is limited signal margin in voltage domain when supply voltage is fixed, which may cause accuracy penalty.…”

Section: A Sram-cim Chip Architecturementioning

confidence: 99%

“…CIM accelerators implemented in prior works using SRAM [2]- [9] as basic processing cell have shown great potential for CNN inference. However, there are still several concerns to be noted.…”

Section: Introductionmentioning

confidence: 99%

Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators

Wang

Zou

Zheng

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents an architectural framework and an evaluation model for Static Random Access Memory (SRAM)-based Computing-in-Memory (CIM) edge Convolutional Neural Network (CNN) accelerators. To provide a baseline for system-level design perspectives, an architectural framework for SRAM-CIM design concerning the key design points in state-of-the-art works is proposed. Furthermore, a configurable evaluation model featuring top-down design flow based on the proposed framework is established to investigate design space explorations. Case studies validated the framework and evaluation model using LeNet-5, AlexNet and VGG-16 to achieve energy-aware optimizations. The optimized memory scale for LeNet-5 is "16 PEs and 120 tiles" with the minimal estimated inference energy of 0.0018μJ, while for AlexNet and VGG-16, "16 PEs and 120 tiles" is better achieving minimal energy consumption of 0.1733mJ and 0.6825mJ respectively. Estimation results highlight tradeoffs among data representtation parameters and memory partitioning parameters. This work provides specific SRAM-CIM design guidelines from a system-level perspective.

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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Cited by 140 publications

References 2 publications

Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor

Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor

When wearable technology meets computing in future networks

Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators

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