15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16&amp;#x00D7; spatial redundancy in 14nm FinFET technology

Kim, Sungjin; Kim, Woo Seok; Song, Minyoung; Kim, Jihyun; Kim, Tae-Ik; Park, Ho‐Jin

doi:10.1109/isscc.2015.7063035

Cited by 39 publications

(16 citation statements)

References 3 publications

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“…The goal was to minimize the interpolation error by multiple-sampling of nonrelated errors, which would partly compensate each other and thus improve the single-shot precision. The idea is not totally new [23], [26], but here the realization is totally different and the multi-sampling is combined to the linear Nutt-based architecture, which makes ps-level precision possible in a wide measurement range.…”

Section: Tdc Based On Systematic Internal Averagingmentioning

confidence: 99%

Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

Jansson

Keränen

Jahromi

et al. 2020

IEEE Trans. Instrum. Meas.

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A time-to-digital converter (TDC) often consists of sophisticated, multilevel, subgate delay structures, when time intervals need to be measured precisely. The resolution improvement is rewarding until integral nonlinearity (INL) and random jitter begins to limit the measurement performance. INL can then be minimized with calibration techniques and result postprocessing. The TDC architecture based on a counter and timing signal interpolation (the Nutt method) makes it possible to measure long time intervals precisely. It also offers an effective means of improving precision by averaging. Traditional averaging, however, demands several successive measurements, which increases the measurement time and power consumption. It is shown here that by using several interpolators that are sampled homogeneously over the clock period, the effects of limited resolution, interpolation nonlinearities, and random noise can be markedly reduced. The designed CMOS TDC utilizing internal systematic sampling technique achieves 3.0-ps root mean square (RMS) single-shot precision without any additional calibration or nonlinearity correction. Index Terms-Averaging, CMOS, delay-locked loop (DLL), integral nonlinearity (INL), jitter, Nutt method, quantization error, time interval measurement, time-to-digital converter (TDC). I. INTRODUCTION A TIME-TO-DIGITAL converter (TDC) measures the time interval between two or more timing signals and presents the result in digital form. For the sake of simplicity, the timing signals are often called start and stop signals. High precision TDCs are used in many applications, such as laser distance measurement [1], [2], high energy physics [3], [4], timing parameter verification of high-speed circuits and components [5], [6], medical imaging [7], [8], single-photon detectors [9], [10], and Raman spectroscopy [11], [12]. The use of TDC techniques is increasing as traditional analog signal processing is challenged by modern scaled IC-circuit technologies, which favor signal processing in the time domain. The critical analog circuit blocks can be often replaced with a TDC-based architecture in all-digital PLLs [13], [14] and in analog-to-digital conversion (ADC) [15], [16], for example.

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Section: Tdc Based On Systematic Internal Averagingmentioning

confidence: 99%

Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

Jansson

Keränen

Jahromi

et al. 2020

IEEE Trans. Instrum. Meas.

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“…The resolution of Vernier TDCs can be an order of magnitude higher when compared with that of their flash counterparts. The large variation of per-stage-delay caused by process uncertainty, however, severely limits their ability to achieve a high resolution [1]. Although delta-sigma operations are capable of yielding a high resolution, the unavailability of high-order time integrators presently impose a stiff challenge in the realisation of high-order delta-sigma TDCs needed for achieving a high resolution [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

Lee

Yuan

Khan

et al. 2021

IET Circuits, Devices & Systems

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This study presents an 8-bit delay line digital-to-time converter (DTC) with pre-skewing and digital time interpolation. Pre-skewing that lowers the per-stage-delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri-state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post-layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μW.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…On the other hands, the performance of analog ICs designed with advanced CMOS process are limited by low intrinsic device gains, large leakage current and low supply voltage. Therefore, digital implementations of analog and mixed signal ICs become more and more attractive [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

Yang

Zhao

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm 2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc. Keywords synthesized all-digital phased-locked loops (ADPLL), bang-bang phased-locked loop (BBPLL), automatically placed & routed (APR), output feedback DAC (OFDAC), injection-locked Citation Yang J C, Zhang Z, Qi N, et al. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.

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15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology

Cited by 39 publications

References 3 publications

Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

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