2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers 2015
DOI: 10.1109/isscc.2015.7063026
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14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster

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Cited by 20 publications
(13 citation statements)
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“…Cache viruses were crafted to exploit the underlying microarchitecture and test all levels of the cache hierarchy, while core viruses are being generated by genetic algorithms. To stress the cores, we use dI/dt viruses that cause the CPU power consumption to switch between high and low power at a rate equal to PDN 1 st order resonant frequency [2,8,14]. This causes maximum voltage noise.…”
Section: Cstress-test Developmentmentioning
confidence: 99%
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“…Cache viruses were crafted to exploit the underlying microarchitecture and test all levels of the cache hierarchy, while core viruses are being generated by genetic algorithms. To stress the cores, we use dI/dt viruses that cause the CPU power consumption to switch between high and low power at a rate equal to PDN 1 st order resonant frequency [2,8,14]. This causes maximum voltage noise.…”
Section: Cstress-test Developmentmentioning
confidence: 99%
“…Such margins are becoming more prominent with the use of more cores per chip and technology scaling. These technology trends exacerbate core-to-core variations, voltage droops [2,3], reliability issues [2] and SRAM malfunctions [15,16] at low voltages (Vmin).…”
Section: Introductionmentioning
confidence: 99%
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