12-Bit Pipeline ADC Implemented in 0.09-um Digital CMOS Technology for Powerline Alliance

Abstract

This paper presented its own design of 12-bit pipeline ADC which has an operating frequency of 8 MHz and consists of 4 stages only. This design is a pipelined ADC with four 3-bit stages (each stage resolves two bits).By doing so, the chip area can be decreased along with minimized power dissipation. In the study's design, V IN , is first sampled and held steady by a sample-and-hold (S&H), while the flash ADC in stage one quantizes it to three bits. The 3-bit output is then fed to a 3-bit DAC (accurate to about 12 bits), and the analog output is subtracted from the input. This "residue" is then gained up by a factor of four and fed to the next stage. This gained-up residue continues through the pipeline, providing three bits per stage until it reaches the 4bit flash ADC, which resolves the last 4LSB bits. Because the bits from each stage are determined at different points in time, all the bits corresponding to the same sample are time-aligned with shift registers. Index Terms-pipeline ADC, time alignment, shift registers, multiplying DAC, flash ADCs, full adder, half adder, delay I. INTRODUCTION Power Line Communication (PLC) represents an exceptionally promising alternative for high-speed internet access and data networking.PLC is one of today's outstanding technology for communication systems that allows data transfer over existing power cables. [1] This means that, with just power cables running to an electronic device (for example), one can power it up and at the same time control and retrieve data from it in a half-duplex manner. Powerline alliance is made possible by high-speed analog-to-digital converters (ADC). ADCs translate analog quantities, which are characteristic of most phenomena in the "real world," to digital language, used in information processing, computing, data transmission, and control systems. [2] Pipeline analog-to-digital-converters offer a wide range of advantages compared to other topologies, notably optimum balance of size, speed and resolution. A pipelined ADC employs a parallel structure in which each stage works on one to a few bits of successive samples Manuscript