(110) Ultrathin GOI layers fabricated by Ge condensation method

Dissanayake, Sanjeewa; Shuto, Yusuke; Sugahara, Satoshi; Takenaka, Mitsuru; Takagi, Shinichi

doi:10.1016/j.tsf.2008.08.102

Cited by 26 publications

(26 citation statements)

References 3 publications

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“…As for p-MOSFETs, a (110) Ge surface is known to provide the highest hole mobility. We have recently succeeded in fabricating (110) GOI structures just by using (110) SOI substrates as starting materials in the Ge condensation process [33]. We have confirmed the device operation of (110) GOI p-MOSFETs under back gate control and a hole mobility enhancement of around 1.4-2.8x against the Si universal hole mobility has been obtained [34,35].…”

Section: (110)mentioning

confidence: 67%

High mobility channel CMOS technologies for realizing high performance LSI's

Takagi

2009

2009 IEEE Custom Integrated Circuits Conference

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Saturation of CMOS performance has been evident in the present 45/32 nm technology node, because of a variety of physical limitations on the miniaturization. Thus, channel engineering, including the enhancement of drive current due to high mobility channel materials and with robustness against short channel effects and characteristic variation due to multi-gate structures, has currently been recognized as mandatory for high performance CMOS. In this paper, we report our approaches to further improvement of MOSFETs by using strained-Si, SiGe, Ge and III-V semiconductor channels on the Si CMOS platform with an emphasis on the combination of ultra-thin body and multi-gate structures. IntroductionThe device scaling concept, which can lead to the increase in both the switching speed and the number density of MOSFETs under reasonable power consumption, had been the main guiding principle of the MOS device engineering over these thirty years. It has been recognized, however, below 32 nm technology node that this conventional device scaling has confronted the difficulty that the three main indices associated with MOSFET performance, on-current, power consumption and short channel effects, have the trade-off relationship with each other, owing to several physical and essential limitations directly related to the device miniaturization, such as tunneling current, mobility reduction, source/drain resistance, inversion-layer capacitance and Sub-threshold slope.Fig. 1 Schematic log I ds -V g characteristics to show the factor affecting power consumption.Fig. 1 shows a schematic Id-Vg curve of MOSFETs.Here, the power consumption, P consum , and the on current, I on , can be roughly described [1] bywhere a, f, C load , I 0 , S, I leak , N s , C g and υ are a constant value, the operating frequency, the load capacitance, the drain current at V g of V th , the Sub-threshold slope, the total leakage current including gate and junction leakages, the induced surface carrier concentration in the channel, the gate capacitance and the velocity near the source region, respectively. In order to realize low power MOSFETs, lower V dd , higher V th , smaller S (higher immunity to short channel effects) and lower I leak are necessary. However, these requirements clearly conflict with high I on , which is still important for signal processing. Also, these requirements pose severe trade-off relationship on choosing device parameters like gate oxides thickness, T ox , substrate impurity concentration, N sub , meaning that it is physically difficult to further improve the performance and power consumption under the conventional Si CMOS scheme. Source Engineering Gate Stack Engineering metal gate high k Channel Engineering SOI Strained Si, Ge, III-V Back gate, Fin Structure, Double gate, Nano-wire etc. Mobility, velocity, ballistic transport Carrier injection velocity Ultra-shallow junction, source resistance, metal S/D Suppression of SCE EOT Inversion-layer thickness Steep impurity profileFig. 2 Schematic diagram of three types of device enginee...

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Section: (110)mentioning

confidence: 67%

High mobility channel CMOS technologies for realizing high performance LSI's

Takagi

2009

2009 IEEE Custom Integrated Circuits Conference

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“…Thus, the SiGe layer is transformed into Ge. (110)-oriented compressively strained (1.1%) GeOI layers with Ge thickness of 12 nm have been demonstrated [18]. This is not as popular as other techniques for integrating Ge on Si, which is somewhat surprising as it is relatively straight-forward.…”

Section: Substrates and Integrationmentioning

confidence: 99%

Processing of germanium for integrated circuits

Duffy¹,

Shayesteh²,

Yu³

2014

Turk J Phys

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Abstract:In this review paper the authors will focus on Ge processing for integrated circuits. The key areas that require the most attention are substrates and integration, gate dielectrics, and access resistance. We will discuss each of these topics in turn, while also reviewing the most scaled Ge field-effect-transistor devices, and consider how modelling activities have matured for Ge in recent years.

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“…Therefore, it is theoretically quite difficult to develop process technologies to reduce the dislocation density in the Ge layer grown directly on the Si. Another approach to fabricating single-crystal Ge with low dislocation density is Ge condensation [4,5] by thermally oxidizing SiGe grown thinner than the critical thickness on Si. Condensation of Ge is realized by selectively oxidizing Si atoms and increasing the atomic contents of Ge in SiGe [4,5].…”

Section: Introductionmentioning

confidence: 99%

“…Another approach to fabricating single-crystal Ge with low dislocation density is Ge condensation [4,5] by thermally oxidizing SiGe grown thinner than the critical thickness on Si. Condensation of Ge is realized by selectively oxidizing Si atoms and increasing the atomic contents of Ge in SiGe [4,5]. In the Ge condensation technique [4,5], compressive strain is applied to the interface between the buried oxide (BOX) and condensed Ge layers, which results in an increase in the energy difference between the indirect L valley and the direct Γ valley in the conduction band [6].…”

Section: Introductionmentioning

confidence: 99%

“…Condensation of Ge is realized by selectively oxidizing Si atoms and increasing the atomic contents of Ge in SiGe [4,5]. In the Ge condensation technique [4,5], compressive strain is applied to the interface between the buried oxide (BOX) and condensed Ge layers, which results in an increase in the energy difference between the indirect L valley and the direct Γ valley in the conduction band [6]. Therefore, device structures and process technologies must be improved to enhance light emission efficiency.…”

Section: Introductionmentioning

confidence: 99%

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Ge(111)-fin light-emitting diodes

Tani

Saito

Oda

et al. 2011

8th IEEE International Conference on Group IV Photonics

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Ge quantum wells perpendicular to a substrate, called Ge fins, have been fabricated by selectively oxidizing Si in SiGe grown epitaxially on an atomically flat Si(111) surface. The three-dimensional structure of the fins is suitable for relaxing the compressive strain induced by the lattice constant mismatch between the Si and Ge. The current voltage characteristics of Ge diodes show low dark currents, confirming the high crystalline quality of the Ge fins. By injecting forward currents into the Ge fins, we found direct recombinations at the Γ valley.

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(110) Ultrathin GOI layers fabricated by Ge condensation method

Cited by 26 publications

References 3 publications

High mobility channel CMOS technologies for realizing high performance LSI's

High mobility channel CMOS technologies for realizing high performance LSI's

Processing of germanium for integrated circuits

Ge(111)-fin light-emitting diodes

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