110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock

Takahashi, Tsuyoshi; Muto, Takashi; Shirai, Y.; Shirotori, F.; Takada, Y.; Yamagiwa, A.; Nishida, A.; Hotta, A.; Kiyuna, T.

doi:10.1109/4.799856

Cited by 10 publications

(6 citation statements)

References 8 publications

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“…After the sense-amp operation, the original data packets and are recovered. Detailed transceiver circuit design, orthogonal coding, and the reconfigurable I/O operation are explained in Section V. We can also apply this SSCDMA-I to simultaneous bidirectional signaling (SBD) on a point-to-point link, assuming that the length of the physical transmission channel is well matched with the transmission cycle time (or bandwidth) to avoid eye distortion which is common in all conventional SBD schemes [15].…”

Section: B Dual Concurrent Transactions For Advanced Parallelism Andmentioning

confidence: 99%

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

Kim

Verbauwhede

Chang

2007

IEEE Trans. VLSI Syst.

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The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SS- CDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SS-CDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requestsand by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-m CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os. Index Terms-Bandwidth, bus, input/output (I/O) interface, inter-chip communication, interconnect, latency.

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Section: B Dual Concurrent Transactions For Advanced Parallelism Andmentioning

confidence: 99%

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

Kim

Verbauwhede

Chang

2007

IEEE Trans. VLSI Syst.

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“…Conventionally, to extract the far-end information, adaptive interference cancellers in such links may require a foreground training and a phase locked arrangement [12], [18], [24], [25]. Whereas, the proposed TFD-IO because of the correlationbased SI-canceller can adapt its weights in presence of the far-end signal.…”

Section: A Same Baud-rates and Signalling Schemesmentioning

confidence: 99%

“…These hybrids may also require manual tuning or foreground calibration to support data transfer over a wide range of interface conditions. Furthermore, most of these techniques require timing synchronization between the two transceivers, to ensure that the interference is suppressed/cancelled sufficiently, as the amount of cancellation depends on the receiver sampling phase [12], [18], [24], [25]. To overcome the above mentioned limitations, digital techniques have to be implemented, which can support interference cancellation adaptively [17].…”

Section: Introductionmentioning

confidence: 99%

A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

Goyal¹,

Gupta²,

Parulekar³

2021

Preprint

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In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) and echoes adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8 Gb/s.

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“…These hybrids may also require manual tuning or foreground calibration to support data transfer over a wide range of interface conditions. Furthermore, most of these techniques require timing synchronization between the far-end and the near-end signals, to ensure that the interference is suppressed/cancelled sufficiently, as the amount of cancellation depends on the receiver sampling phase [19], [20], [30], [31]. To overcome the above mentioned limitations, digital techniques have to be implemented, which can support interference cancellation adaptively [18].…”

Section: Introductionmentioning

confidence: 99%

A True Full-Duplex IO (TFD-IO) with Background SI Cancellation for High-Density Interfaces

Goyal¹,

Parulekar²,

Gupta³

2021

Preprint

View full text Add to dashboard Cite

In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. <br>The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud-rates and signaling schemes in a TFD-IO. A proof-of-concept design of the TFD-IO module has been fabricated in a 65 nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8\,Gb/s.

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110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock

Cited by 10 publications

References 8 publications

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

A True Full-Duplex IO (TFD-IO) with Background SI Cancellation for High-Density Interfaces

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