2021 IEEE International Solid- State Circuits Conference (ISSCC) 2021
DOI: 10.1109/isscc42613.2021.9365852
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11.8 An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS

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Cited by 10 publications
(5 citation statements)
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“…Furthermore, most of these techniques require timing synchronization between the far-end and the near-end signals, to ensure that the interference is suppressed/cancelled sufficiently, as the amount of cancellation depends on the receiver sampling phase [19], [20], [30], [31]. To overcome the above mentioned limitations, digital techniques have to be implemented, which can support interference cancellation adaptively [18]. However, implementing SI cancellation using digital approaches is often power and area inefficient.…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, most of these techniques require timing synchronization between the far-end and the near-end signals, to ensure that the interference is suppressed/cancelled sufficiently, as the amount of cancellation depends on the receiver sampling phase [19], [20], [30], [31]. To overcome the above mentioned limitations, digital techniques have to be implemented, which can support interference cancellation adaptively [18]. However, implementing SI cancellation using digital approaches is often power and area inefficient.…”
Section: Introductionmentioning
confidence: 99%
“…To achieve higher throughputs, recent high-speed FD interconnects use hybrids with active circuits for interference suppression [11], [12], [16]- [20]. These hybrids effectively consist of one of the following: (i) a scaled replica generator with a subtractor [17]; (ii) a comparator with dynamic referencing [18], [21], [22]; (iii) a resistive or a capacitive bridge [11], [19]; (iv) a resistor-transconductor (Rgm) cell [12], [16]; and (v) a directional inverter/buffer (DIB) with weighted cancellation paths [23]. The main limitation in these schemes is that the AFEs do not account for the delay spread of the transmitted pulses that causes SI over multiple bit periods.…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, most of these techniques require timing synchronization between the two transceivers, to ensure that the interference is suppressed/cancelled sufficiently, as the amount of cancellation depends on the receiver sampling phase [12], [18], [24], [25]. To overcome the above mentioned limitations, digital techniques have to be implemented, which can support interference cancellation adaptively [17]. However, implementing interference cancellation using digital approaches need a high resolution analog-to-digital converter, thus is often power and area inefficient [13], [17].…”
Section: Introductionmentioning
confidence: 99%
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“…To overcome the above mentioned limitations, digital techniques have to be implemented, which can support interference cancellation adaptively [18]. However, implementing SI cancellation using digital approaches is often power and area inefficient.…”
mentioning
confidence: 99%