100 V class multiple stepped oxide field plate trench MOSFET (MSO-FP-MOSFET) aimed to ultimate structure realization

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

“…Therefore, a higher resistivity bottom EPI spec is required to sustain a high rating voltage that results in a higher R on than the triple-EPIs design. Compared with other methods mentioned in [15,[18][19][20][21], the multiple-EPIs structure does not complicate the process in manufacturing, and a higher-V BR and a lower-R on,sp device can be achieved. We also use the same method to construct 200 V SGT devices with different EPI designs.…”

“…Figure 12 compares the specific on-resistance performance of our proposed SGT devices with that of the other middle-voltage devices reported in [4,15,21,[32][33][34][35][36][37][38][39][40], ideal silicon limit, and super junction (SJ) limit for cell pitch = 5 and 10 µm in the 50-200 V range. Form Figure 12, we observe that the triple-EPIs structure and those using a double split-gate device [15] and stepped oxide SGTs [18,20,21] can achieve a very low R on,sp in the middle-voltage range because they all can maintain more uniform EF distributions between two trenches. Compared with a double split-gate device and stepped oxide ones, our triple-EPIs devices do not require the complicated double split-gate or oxide-engineering process in the trenches and is compatible with the conventional SGT process.…”

“…When the device rating voltage reaches 150-200 V, the drift resistance occupies about 90% of the total device resistance [16,18]. To achieve a high breakdown voltage (V BR ) design without increasing the R on too much, a gradient, two-stepped oxide or multiple stepped oxide designs were applied to the trenches and shown to improve device performance effectively [18][19][20][21]. Since the potential of the field plate (bottom gate) on the oxide around it is different everywhere, that leads to a different depletion strength and electric field between two trenches along the cell depth, [18][19][20][21] use oxide engineering to improve device performance.…”

“…To achieve a high breakdown voltage (V BR ) design without increasing the R on too much, a gradient, two-stepped oxide or multiple stepped oxide designs were applied to the trenches and shown to improve device performance effectively [18][19][20][21]. Since the potential of the field plate (bottom gate) on the oxide around it is different everywhere, that leads to a different depletion strength and electric field between two trenches along the cell depth, [18][19][20][21] use oxide engineering to improve device performance. On the other hand, double split-gate resurf stepped oxide UMOS can overcome the non-uniform problem [15]; however, the oxide and poly process in the trenches is too complicated.…”

“…This unique merit allows for the possibility of the double-EPIs design to reduce R on,sp , as well as its power consumption. In this study, we wanted to design and modify the EPI structures rather than the complicated fabrication ways mentioned in [15,[18][19][20][21], to reduce device R on and sustain a high V BR at the same time. When device ranting voltage is designed to over 100 V, we find that the R on of double-EPIs structure is no longer satisfying our expectations.…”