100 Mpixel/sec single-chip integrated graphics controller (IGC)

Abstract

The IGC is a single-chip 2-D raster graphics engine for 1-2M pixel, 8-bit pseudorealistic color desktop systems. With on-chip controllers for video, RAMDAC, and interleaved VRAMs, together with dedicated hardware for scan-conversion, image and block transfers, clipping and raster operations, the 185K transistor, 208-pin custom IC operates at 25MHz at full 1-Mbit VRAM bandwidth of 100 megapixeWsecond. o d u c mSophisticated windowing user interfaces coupled with high color monitor resolution place stringent demands on performance and cost of graphics hardware, particularly for low-end workstations and high-end personal computers. The IGC cost-effectively meets the requirements of fast display management ( Fig. 1) by taking over and accelerating many routine but time-consuming jobs from the graphics software such as memory and screen blits, text drawing, line drawing, and filling of quadrilateral tiles (in both X-11 and Bresenham modes).The IGC pipeline consists of the host bus interface, the coordinate processing engine, the drawing engine, and the frame buffer and video controllers (Fig. 2). The pipeline performs all functions at the maximum bandwidth of the dual-bank, interleaved pixmap built from loons, 1-Mbit, split-shift VRAMs. Interlock hardware stalls the pipeline whenever a stage cannot support the peak pipeline rate of 100Mpixels/sec. v The IGC operates as a memory-mapped peripheral. All host accesses to the IGC are, therefore, simple reads and writes to a 22-bit address space. The upper half of this space is the display memory, on which the host can perform direct dumb frame buffer accesses. The lower half is decoded into instructions to access the IGC registers and initiate the drawing commands.The drawing operations supported are quadrilateral fills (the quad command), host-to-screen transfers of pixel image in monochrome (the pixell command) or color (the pixel8 command), screen-to-screen bit block transfers (the blit command) and rendering the consecutive 16.3.1 IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE CH2994-2/91/0000/0093 $1.00 1991 IEEE pixel1 and pixel8 operations to the next area of the frame buffer (the nextqixels command).The host interface directly accepts address, data and clock signals of either multiplexed or non-multiplexed, synchronous or asynchronous system buses. A 32-bit shifter corrects any endian-ness incompatibility between the host and the IGC. The lower two bits of the address in conjunction with two other input pins provide 16 combinations in which the four bytes of the 32-bit data can be written during a pixel map write operation.The write operations (pixell and pixel8 commands) complete in a relatively small number of cycles and the IGC hangs the bus until the operation is complete. The read operations (quad and blit commands) could take a large number of cycles, therefore, the host interface ignores any read commands until the previous operation is complete. Both polling and interrupt-driven techniques are supported for the application program to query and continue exe...