2009
DOI: 10.1109/jssc.2009.2026819
|View full text |Cite
|
Sign up to set email alerts
|

100 GHz+ Gain-Bandwidth Differential Amplifiers in a Wafer Scale Heterogeneously Integrated Technology Using 250 nm InP DHBTs and 130 nm CMOS

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
4
0

Year Published

2013
2013
2017
2017

Publication Types

Select...
5
1

Relationship

0
6

Authors

Journals

citations
Cited by 9 publications
(4 citation statements)
references
References 6 publications
0
4
0
Order By: Relevance
“…(10) indicates that the bipolar detector responsivity increases with the device bias current. Figure 4 shows a detector schematic designed in an InP HBT technology, supported by HRL Laboratories [22]. The InP device peak f T is about 350 GHz when the collector bias current is about 6mA and the f T drops to about 70 GHz with 100 µA collector bias current [22].…”
Section: B Bipolar Power Detectormentioning
confidence: 99%
See 1 more Smart Citation
“…(10) indicates that the bipolar detector responsivity increases with the device bias current. Figure 4 shows a detector schematic designed in an InP HBT technology, supported by HRL Laboratories [22]. The InP device peak f T is about 350 GHz when the collector bias current is about 6mA and the f T drops to about 70 GHz with 100 µA collector bias current [22].…”
Section: B Bipolar Power Detectormentioning
confidence: 99%
“…Figure 4 shows a detector schematic designed in an InP HBT technology, supported by HRL Laboratories [22]. The InP device peak f T is about 350 GHz when the collector bias current is about 6mA and the f T drops to about 70 GHz with 100 µA collector bias current [22]. This technology supports both InP and Silicon BiCMOS devices by intimately integrating InP HBT devices together with deep scaled CMOS devices.…”
Section: B Bipolar Power Detectormentioning
confidence: 99%
“…Once bonded, the temporary handle wafer is removed and subsequent InP DHBT and heterogeneous interconnect processing starts. Additional details concerning fabrication and processing can be found in [8,9].…”
Section: Inp/si Bicmos Integrationmentioning
confidence: 99%
“…It would be advantageous to combine the merits of both compound semiconductors and silicon based CMOS/BiCMOS in order to enable a new class of high performance ICs (5) while allowing the rapid adoption of more advanced CMOS and compound semiconductor technology generations. This work will review HRL's efforts in wafer scale integration of an advanced 250nm, 350GHz fT/fMAX InP DHBT technology (6) with RF-CMOS technologies whose device proximity; heterogeneous interconnect density; and additional technology features both leverage and provide additional value to conventional silicon technologies (7),( 8),( 9), (10), (11), (12).…”
Section: Introductionmentioning
confidence: 99%