Radiation-induced errors in memory chips

Abstract

We have measured probabilities for proton, neutron and pion beams from accelerators to induce temporary or soft errors in a wide range of modern 16 Mb and 64 Mb DRAM memory chips, typical of those used in aircraft electronics. Relations among the cross sections for these particles are deduced. Measurement of alpha particle yields from pions on aluminum, as a surrogate for silicon, indicate that these reaction products are the proximate cause of the charge deposition resulting in errors. I IntroductionIn 1978 a serious industrial problem was causing errors in the memory contents of Intel 2107 16Kb DRAM (Dynamic Random Access Memory) chips.[1] These temporary or soft errors did not damage the chip, but an erroneous 'zero' had replaced a 'one', or vice versa, spoiling the contents of the memory. This problem was traced to small amounts of alpha-emitting impurities in the materials. These 5 MeV alpha particles caused ionization in the Si of the chip, and the collected charge was enough to redefine the memory state.Later, in repair records from 1984, IBM found a correlation between these errors, here called 'soft error upsets' or SEU, and altitude. These errors were then shown to be closely correlated with cosmic ray intensities. [2,3] In Denver, at 1700m, the SEU rate was ten times the national average.It is easy to understand how heavily-ionizing low energy alpha particles, with a range of 25 microns in Si, could deposit disruptive charge, but how would high energy neutrons, protons and pions from cosmic ray reactions induce errors? At sea level, most cosmic rays are muons, with only small cross sections for any reactions, but evidently energetic hadrons can cause reactions within microcircuits to produce short range heavily ionizing reaction products.A series of experiments with intense accelerator beams has been used to measure the probabilities or cross sections for hadrons to induce SEU in a wide range of modern memory chips. These measurements are particularly important for commercial and military aircraft, with their high altitude operations.Here we define σ SEU = induced errors number of sample bits × particles/cm 2 . II Accelerator testingCommercially available memory chips were placed directly in our beams. Proton beams were mostly from the Harvard cyclotron, at energies from 50 to 150 MeV. III ComparisonsSEU cross sections for 16 Mb samples showed a very wide range, strongly dependent upon the chip construction. Cross sections are shown in Fig. 2. For some manufacturers, several different chips of the same model were studied, with little scatter. The large differences can be explained by the smaller volume of Si available to deposit stray charge in the newer generations.

A Distributed System for Radiation Monitoring at Linear Accelerators

“…Neutrons present in the accelerator's chamber provoke SEUs in an SRAM chip [19]- [21]. A random bit-pattern must be written into the memory chip before the measurement process starts.…”

<title>DSP-based system for advanced radiation tolerant algorithms evaluation</title>

“…This leads to a current spike that can have an important influence on the electronic system. For example, in a SRAM memory cell, this can cause a bit-flip [13].…”

A distributed System for Radiation Monitoring at Linear Accelerators

“…Neutrons present in the accelerator's chamber provoke SEUs in a SRAM chip [19]- [21] . A random bit-pattern must be written into the memory chip before the measurement process starts.…”