Analog Electronic Circuit Synthesis Using Simulated Annealing and Geometric Circuit Evolution

Abstract

This article presents the SANN-GCE algorithm, a spice simulation driven meta-heuristic to design general discrete analog electronic circuits automatically, both circuit topology and component sizing. We introduce an encoding scheme called Geometric Circuit Evolution (GCE) that works associated with the Simulated Annealing algorithm and uses categorized degrees of freedom, that allows distinct characteristics of a circuit to change with different probabilities according to its type during the circuit evolution. We show through a series of seven active test circuits that SANN-GCE, compared to a benchmark, present a median fitness 15.88 times better, with a median standard deviation 6.72 times lower between runs. The median runtime found was 14.17 times lower.