10-Channel Very Low Noise Eng Amplifier System Using Cmos Technology

Rieger, Robert; Pal, Dipankar; Taylor, J.; Clarke, Chris; Langlois, P.J.; Donaldson, Nick

doi:10.1109/iscas.2005.1464696

Cited by 6 publications

(6 citation statements)

References 8 publications

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“…Bipolar transistors exhibit a very low noise floor and also the flicker-noise contribution is typically smaller than that of MOS transistors. Lateral bipolar transistors, which can be manufactured in a conventional CMOS process, have been demonstrated to be a practical alternative to vertical devices which require a more costly BiCMOS process [3,29].…”

Section: Low-noise Amplifiersmentioning

confidence: 99%

“…Also, recently reported amplifier circuits are near to approaching the optimum efficiency of 2. Highest performance is achieved using bipolar transistors [3,28,29], even if non-ideal devices such as lateral structures are employed [3,29]. MOS stages operating in weak inversion mode can also approach the limiting value of 2 although the devices tend to be very large and hence more restricted in bandwidth than the bipolar/lateral bipolar option [4,28,51].…”

Section: Low-noise Amplifiersmentioning

confidence: 99%

“…It is observed that single amplifiers are available exhibiting a performance not far from the optimum figure of 2 [28,51] and that MCRA exhibit slightly lower efficiency. It is only recently that a 10-channel system has been reported using lateral bipolar input transistors, which achieves a near optimum noise efficiency [3,29]. As explained in Sect.…”

Section: Input Offset Rangementioning

confidence: 99%

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Design strategies for multi-channel low-noise recording systems

Rieger

Taylor

2008

Analog Integr Circ Sig Process

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Parallel recording of micro-scale signals using an integrated system approach has become feasible with recent advances in technology. Practical applications include the recording of neural-signals in a brain-computer interface or in prosthetic implants. In an integrated circuit implementation the restriction in size and available power pose considerable challenges, especially in implanted devices. Furthermore, the provision of both high gain and excellent noise performance in the presence of input offset voltages are mandatory. The presented tutorial highlights design strategies for recording system optimization and compares the performance of actual system implementations with the best-case performance achievable in theory. Special consideration is given to the noise vs. power and offset-tolerance vs. noise trade-offs. An application dependent design strategy is proposed.

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Section: Low-noise Amplifiersmentioning

confidence: 99%

Section: Low-noise Amplifiersmentioning

confidence: 99%

Section: Input Offset Rangementioning

confidence: 99%

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Design strategies for multi-channel low-noise recording systems

Rieger

Taylor

2008

Analog Integr Circ Sig Process

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“…Donaldson et al reported successive generations of very low-noise amplifier chips suitable for interfacing with extrafascicular electrodes (e.g., nerve cuff electrodes) [29, 105, 107, 134]. Recent studies have reported neural amplifiers [107, 134] that employ the velocity selection recording (VSR) technique, first proposed in [106], to selectively amplify weak PNS signals with differing conduction velocities. The ability of VSR to discriminate recorded activity based on fiber type has been validated in several acute in vivo studies [123, 124, 153]; demonstrating this technique in a chronically implanted model would represent a major advancement.…”

Section: Applications Of Neural Amplifiersmentioning

confidence: 99%

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Greenwald

et al. 2016

Med Biol Eng Comput

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Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

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“…This has a sampling rate of 100 ks/s which, as already noted, provides a channel sampling rate of 10 ks/s and oversampling rate of about four times for a channel bandwidth of 2.5 kHz. However it has become apparent that in order to take full advantage of the capabilities of VSR, a wider analogue bandwidth is desirable which inevitably influences the choice of ADC [17,23]. In order to maintain a four times oversampling rate with a channel bandwidth of 10 kHz, an ADC sampling at 400 ks/s is required.…”

Section: Analogue Bandwidthmentioning

confidence: 99%

An implanted system for multi-site nerve cuff-based ENG recording using velocity selectivity

Clarke

Rieger

et al. 2008

Analog Integr Circ Sig Process

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This paper describes the design of an implantable system for velocity-selective electroneurogram (ENG) recording. The system, which relies on the availability of multielectrode nerve cuffs (MECs) consists of two CMOS ASICs. One ASIC called the electrode unit (EU) is a mixed analogue/digital signal acquisition system which is mounted directly on an MEC in order to optimize the interface between the two. It is linked to the other ASIC by means of a 5-core cable through which it receives power and commands in addition to transmitting data. The second ASIC, called the monitoring unit (MU) manages the interface between the EUs (each MU can control up to three EUs) and an RF transcutaneous link to the external signal processor. The ASICs are fabricated in 0.8 lm CMOS technology. The EUs measure 3 mm 9 4 mm each and consume 105 mW (35 mW each), while the MU measures 1.5 mm 9 2 mm and consumes 4 mW. The power consumption on the communication channels (including cable losses) between the MU and EUs is 129 mW. A digital communication strategy between the two parts of the implanted system and the external controller is described.

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10-Channel Very Low Noise Eng Amplifier System Using Cmos Technology

Cited by 6 publications

References 8 publications

Design strategies for multi-channel low-noise recording systems

Design strategies for multi-channel low-noise recording systems

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

An implanted system for multi-site nerve cuff-based ENG recording using velocity selectivity

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