10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

Wang, Alice; Lin, Tsung-Yao; Ouyang, Shichin; Huang, Wei-Hung; Wang, Jidong; Chang, Shu-Hsin; Chen, Shengping; Hu, Chun-Hsiung; Tai, Jim C.; Tan, Koan-Sin; Tsou, Meng-Nan; Lee, Ming-Hsien; Gammie, Gordon; Yang, Chih‐Wei; Yang, Chun-Chuan; Chou, Yeh-Chi; Lin, Shih-Hung; Kuo, Way; Chung, Chi-Jui; Yong, Lee-Kee; Wang, Chia‐Wei; Dia, Kin Hooi; Chien, Chih-Ching; Tsao, You-Ming; Singh, Nitin Kumar; Lagerquist, Rolf; Chen, Chih‐Cheng; Ko, Uming

doi:10.1109/isscc.2014.6757390

Cited by 19 publications

(5 citation statements)

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“…Heterogeneous SMP:The 28nm Renesas electronics quad/octa core mobile application processor [18], ARM big.LITTLE platform, Nvidia Tegra propose combining high performance cores and low power cores with adaptive voltage scaling techniques. Media Tek 28nm heterogeneous mobile processor [32] consisting of ARM Cortex A15 and A7 cores includes several power, thermal and performance optimizations.…”

Section: Related Workmentioning

confidence: 99%

Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy

Tagliavini

Irick

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with CMPs. In order to study customized architectures, we model four customization design points and compare their performance and energy across a number of computer vision workloads. We analyze the limitations of generic architectures and quantify the costs of increasing customization using these micro-architectural design points. This analysis leads us to develop a framework consisting of low-power multi-cores and an array of configurable micro-accelerator functional units. Using this platform, we illustrate data flow and control processing optimizations that provide for performance gains similar to custom ASICs for a wide range of vision benchmarks.

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Section: Related Workmentioning

confidence: 99%

Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy

Tagliavini

Irick

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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“…CF '16 May 16-19, 2016, Como, Italy Heterogeneous System-on-Chip (SoC) architectures [5] are increasingly used to design computing platforms for both mobile devices [11,28] and data centers [13,23]. To achieve energy-efficient high performance, these SoCs integrate many specialized hardware accelerators, which are equipped with private local memories (PLM) [9,20].…”

Section: Introductionmentioning

confidence: 99%

On the design of scalable and reusable accelerators for big data applications

Pilato

Mantovani

et al. 2016

Proceedings of the ACM International Conference on Computing Frontiers

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Accelerators are becoming key elements of computing platforms for both data centers and mobile devices as they deliver energyefficient high performance for key computational kernels. However, the design and integration of such components is complex, especially for Big Data applications where they have very large workloads to elaborate. Properly customizing the accelerators' private local memories (PLMs) is of critical importance. To analyze this problem we design an accelerator for Collaborative Filtering by applying a system-level design methodology that allows us to synthesize many alternative micro-architectures as we vary the PLM sizes. We then evaluate the resulting accelerators in terms of resource requirements for both embedded architectures and data centers as we vary the size and density of the workloads.

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“…However, the potential energy savings of these devices is limited as they cannot adapt to changes in the sensed information content or sensing context, such as the amount/type of acoustic background noise. In the processor design community, such adaptivity to varying operating conditions is actively researched through the concept of hierarchical computing [3]. This work integrates the concept of hierarchical operation with adaptive early data extraction and classification, towards a power-and context-aware information-extraction sensor interface.…”

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confidence: 99%

24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector

Badami

Lauwereins

Meert

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

Cited by 19 publications

References 1 publication

Exploring architectural heterogeneity in intelligent vision systems

Exploring architectural heterogeneity in intelligent vision systems

On the design of scalable and reusable accelerators for big data applications

24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector

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10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

Cited by 19 publications

References 1 publication

Exploring architectural heterogeneity in intelligent vision systems

Exploring architectural heterogeneity in intelligent vision systems

On the design of scalable and reusable accelerators for big data applications

24.2 Context-aware hierarchical information-sensing in a 6&#x03BC;W 90nm CMOS voice activity detector

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Product

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24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector