1.6 Tbps Silicon Photonics Integrated Circuit and 800 Gbps Photonic Engine for Switch Co-Packaging Demonstration

Fathololoumi, Saeed; Hui, David; Jadhav, S. G.; Chen, Jian; Nguyen, Kimchau N.; Sakib, Meer; Li, Z.; Mahalingam, Hari; Amiralizadeh, Siamak; Tang, Nelson N.; Potluri, Harinadh; Montazeri, Mohammad; Frish, Harel; Defrees, Reece; Seibert, Christopher S.; Krichevsky, A.; Doylend, J. K.; Heck, John; Venables, Ranju; Dahal, Avsar; Awujoola, A.; Vardapetyan, Armen; Kaur, Guneet; Cen, Min; Kulkarni, Vishnutheertha; Islam, S.S.; Spreitzer, R. L.; Garag, S.; Alduino, Andrew; Chiou, RK; Kamyab, Lobna; Gupta, Sanjeev Kumar; Xie, Boping; Appleton, Randal S.; Hollingsworth, Summer R.; McCargar, Sean; Akulova, Y.A.; Brown, K. M.; Jones, Richard E.; Zhu, Daniel; Liljeberg, Thomas; Liao, Ling

doi:10.1109/jlt.2020.3039218

Cited by 103 publications

(39 citation statements)

References 10 publications

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“…This was accomplished either by doubling the number of copper (Cu) input/output (I/O) channels in parallel to the package (which occurred every two years) or by doubling the bandwidth capacity per Cu channel (which occurred every four years) [2]. High performance ToR switch packages have been demonstrated using all electrical I/O with 512 channels, each operating at 106.25 Gbps per channel using the IEEE 802.3-ck standard, yielding a total of 51.2 Tbps per package [3].…”

Section: Introductionmentioning

confidence: 99%

High Density Vertical Optical Interconnects for Passive Assembly

Weninger¹,

Serna²,

Jain³

et al. 2022

Preprint

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The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical's 3D Finite Difference Time Domain solver solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1 𝜇m, 1 dB vertical and lateral alignment tolerances of approximately ± 2.7 𝜇m, a greater than 300 nm 1 dB bandwidth, and 1 dB twist and tilt tolerance of approximately 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.

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Section: Introductionmentioning

confidence: 99%

High Density Vertical Optical Interconnects for Passive Assembly

Weninger¹,

Serna²,

Jain³

et al. 2022

Preprint

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show abstract

“…[ 4,15–17 ] Ever since the invention of the first prototype laser using a QW active region, [ 18 ] millions of transceivers have been shipped in volume in just the last few years, and 1.6 Tbps Si PICs have enabled the first fully functional photonic engine module copackaged with an Ethernet switch. [ 19 ]…”

Section: Introductionmentioning

confidence: 99%

High Speed Evanescent Quantum‐Dot Lasers on Si

Wan

Xiang

Guo

et al. 2021

Laser & Photonics Reviews

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Significant improvements in III–V/Si epitaxy have pushed quantum dots (QDs) to the forefront of Si photonics. For efficient, scalable, and multifunctional integrated systems to be developed, a commercially viable solution must be found to allow efficient coupling of the QD laser output to Si waveguides. In this work, the design, fabrication, and characterization of such a platform are detailed. Record‐setting evanescent QD distributed feedback lasers on Si with a 3 dB modulation bandwidth of 13 GHz, a threshold current of 4 mA, a side‐mode‐suppression‐ratio of 60 dB, and a fundamental linewidth of 26 kHz, are reported. The maximum temperature during the backend III/V process is only 200 °C, which is fully compatible with CMOS process thermal budgets. The whole process is substrate agnostic and hence can leverage previous development in QD lasers grown on Si and benefit from the economy of scale. The broadband and versatile nature of the QD lasers and the Si‐on‐insulator low‐loss waveguiding platform can be expanded to build fully functional photonic integrated circuits throughout the O band.

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“…Recent research has therefore focused on co-integrating silicon photonic devices with electronic components [7]. Various groups have shown either 2D/2.5D integration [8][9][10][11], 3D integration [12][13][14][15][16][17][18][19][20] or monolithic integration [21][22][23][24][25][26][27] to be possible.…”

Section: Introductionmentioning

confidence: 99%

Compact Optical TX and RX Macros for Computercom Monolithically Integrated in 45 nm CMOS

Eppenberger

Bonomi

Moor

et al. 2021

J. Lightwave Technol.

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As the reach of optical communications continues to shrink, photonics is moving from rack-to-rack datacom links to centimeter-scale in-computer applications (computercom) where different architectures are needed. Integrated optical microring resonators (MRRs) are emerging as an attractive choice for fulfilling the more stringent area and efficiency requirements: They offer scaling by wavelength division multiplexing (WDM) and high bandwidth densities. In this paper we present compact electro-optical transmit (TX) and receive (RX) macros for computercom monolithically integrated in 45nm CMOS. They operate with MRR modulators and photodetectors and include all necessary electronics and optics to enable optical links between on-chip data sources and sinks. A most compact implementation for thermal stabilization was enabled by sensing the optical device's bias currents in the driving electronics instead of using external operating point sensing optics. Using a field-effect transistor as heating element -as is possible in monolithic integration platforms -further reduces area and power necessary for thermal control. The TX macro is shown to work for data rates up to 16 Gb/s with a 5.5 dB extinction ratio (ER) and 2.4 dB insertion loss (IL). The RX macro demonstrates a sensitivity of 71 µApp at 12 Gb/s for a BER ≤ 10 -10 . An intra-chip link built with the macros achieves ≤ 2.35 pJ/b electrical efficiency and a BER ≤ 10 -10 at 10 Gb/s. Both macros are realized within 0.0073 mm 2 which amounts to 1.4 Tb/s/mm 2 bandwidth density per macro.

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1.6 Tbps Silicon Photonics Integrated Circuit and 800 Gbps Photonic Engine for Switch Co-Packaging Demonstration

Cited by 103 publications

References 10 publications

High Density Vertical Optical Interconnects for Passive Assembly

High Density Vertical Optical Interconnects for Passive Assembly

High Speed Evanescent Quantum‐Dot Lasers on Si

Compact Optical TX and RX Macros for Computercom Monolithically Integrated in 45 nm CMOS

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