2023
DOI: 10.1109/ted.2023.3295767
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1.2-kV Vertical GaN PIN Rectifier With Ion-Implanted Floating Guard Rings

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Cited by 4 publications
(4 citation statements)
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“…Nitrogen-implanted floating guard rings (FGRs), which have demonstrated effectiveness as an edge-termination technology for kV-class vertical GaN PIN rectifiers, can be used to improve the avalanche breakdown voltage and prevent device failure due to premature breakdown by creating a smooth electric potential and gradient electric field distribution along the junction interface as demonstrated in our previous study. 4,5 Besides the effects of the device edge-termination technique, material defects could also be a detrimental factor in device performance. Surface roughness can cause the incorporation of carbon-related defects and create a more insulating surface region than the bulk.…”
Section: Breakdown Characteristics Analysis Of Kv-class Vertical Gan ...mentioning
confidence: 99%
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“…Nitrogen-implanted floating guard rings (FGRs), which have demonstrated effectiveness as an edge-termination technology for kV-class vertical GaN PIN rectifiers, can be used to improve the avalanche breakdown voltage and prevent device failure due to premature breakdown by creating a smooth electric potential and gradient electric field distribution along the junction interface as demonstrated in our previous study. 4,5 Besides the effects of the device edge-termination technique, material defects could also be a detrimental factor in device performance. Surface roughness can cause the incorporation of carbon-related defects and create a more insulating surface region than the bulk.…”
Section: Breakdown Characteristics Analysis Of Kv-class Vertical Gan ...mentioning
confidence: 99%
“…Details of the device fabrication process and electrical performance were reported in our previous study. 5 To analyze the impact of wafer quality on PIN rectifier breakdown characteristics, confocal PL microscopic mapping was performed at a sub-bandgap excitation wavelength of 405 nm (∼3.06 eV) in device locations prior to the individual PIN device fabrication. An illustration of the PL measurement setup is shown in Fig.…”
Section: Device Fabrication and Sub-bandgap Pl Characterizationmentioning
confidence: 99%
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