0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI

Zhang, Y.; Chen, H.H.; Kuo, J.B.

doi:10.1049/el:20021042

Cited by 28 publications

(12 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…NAND/NOR gates have been implemented using adiabatic logic and it has been reported that adiabatic logic is best suitable for less than 30MHz applications rather than 1MHz or lower applications [11] . A 0.8V CMOS adiabatic differential switch logic circuit has been implemented using bootstrap technique and resulted in 26% less power consumption and 52% smaller propagation delay [12] . A 8 bit carry look ahead adder has been implemented using Energy Recovery Adiabatic Logic Family and 2 to 5 times less dissipative circuit was achieved was achieved [13] .…”

Section: State Of the Artmentioning

confidence: 99%

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Babu¹,

Sivakumar²

2018

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. High speed processors are power consuming and multipliers contribute to a maximum extent for this power consumption. Thus, to achieve low power designs, adiabatic logic is one of the noted technologies in this regard. Adiabatic logic can be implemented for different types of circuit designs and this paper concentrates on a survey of various multipliers and adders that can be modified into a low power multiplier using adiabatic logic.

show abstract

Section: State Of the Artmentioning

confidence: 99%

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Babu¹,

Sivakumar²

2018

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

“…Further, to improve energy efficiency of driver circuits with large capacitive loads, adiabatic technique has been used [10], [11]. Combination of bootstrap and adiabatic techniques has been reported in [12]- [14].…”

Section: Introductionmentioning

confidence: 99%

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Garcia-Montesdeoca

Montiel–Nelson

Nooshabadi

et al. 2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

View full text Add to dashboard Cite

This paper presents the design of an adiabatic/bootstrapped CMOS driver (xb-ad) using complementary pass-transistor logic (CPL) and a four-phase power clock. The proposed xb-ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65nm CMOS 1V technology, under the large capacitive loading condition (16pF), xb-ad performs better than the reference adiabatic circuit (cpl-ad) in terms of active area (64%), and energydelay product (39%). Moreover, xb-ad supports 10 times higher output capacitive load without any additional circuit sizing than cpl-ad.

show abstract

“…After that, a full swing energy efficient logic (eel) [9] circuit was reported to give out a better performance, but the clock system was very complex (it needed eight clocks: four ramp-like power clocks and four pulse clocks) and therefore not practical. A novel adiabatic differential switch logic (adsl) with bootstrap technique introduced in [10] achieved better noise immunity, higher operation frequency and less energy dissipation. The conventional dynamic logic (con), full swing energy efficient logic (eel) and adiabatic differential swing switch logic (adsl) will be power analyzed for security purposes in section 3.3.…”

Section: Introduction To Adiabatic Circuitsmentioning

confidence: 99%

Security wrappers and power analysis for SoC technologies

Gebotys¹,

Zhang²

2003

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign &Amp; System Synthesis - CODES+ISS

Self Cite

View full text Add to dashboard Cite

Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resistance to bus probing attacks, power/EM attacks on cores and network snooping attacks by malicious code are relevant. This paper presents a methodology for security on NoC at both the network level (or transport layer) and at the core level (or application layer) is proposed. For the first time a low cost security wrapper design is presented, which prevents unencrypted keys from leaving the cores and NoC. This is crucial to prevent untrusted software on or off the NoC from gaining access to keys. At the core level (application layer) power analysis attacks are examined for the first time for parallel and adiabatic architectural cores. With the emergence of secure IP cores in the market, a security methodology for designing NoCs is crucial for supporting future wireless internet enabled devices.

show abstract

0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI

Cited by 28 publications

References 3 publications

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Security wrappers and power analysis for SoC technologies

Contact Info

Product

Resources

About