±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

Abstract

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It brings in the benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35µm n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over ±0.5V input range under a nominal supply voltage of ±1.5V, and consumes the total power dissipation of 2.7 mW only.

0.75-V four-quadrant current multiplier using floating gate-MOS transistors

“…This is due to the demand that portable equipments, biomedical devices, bioelectronics and embedded sensor interfaces are increasingly needed. To reduce the power supply voltage, several techniques for designing analog multiplier have been proposed [7]- [ 18]. In [7]- [8], LV /LP analog multipliers were proposed without using special technique, but the circuits in [7] and [8] use the supply voltage of ±l.5 V and l.8 V, respectively.…”

“…To reduce the power supply voltage, several techniques for designing analog multiplier have been proposed [7]- [ 18]. In [7]- [8], LV /LP analog multipliers were proposed without using special technique, but the circuits in [7] and [8] use the supply voltage of ±l.5 V and l.8 V, respectively. In [9]- [10], multiplier circuits using MOS transistors operating in subthreshold region (weak inversion) were proposed while the structures in [11 ]- [ 13] proposed analog multipliers using bulk driven MOS technique.…”