0.5 μm 1 M gate CMOS SOG

Abstract

The one million gates CMOS gate array has been developed by using a half micron three layer-metal CMOS technology. The high speed 1/0 buffers, RAM cell libraries and clock skew management enable to achieve over 100 MHz operating at 3.3V.The gate density of 4.7KG/mm2 and the bit density of 1.8Kbit/mm2 for an asynchronous dual-port RAMS are obtained. The GTL interface cells are prepared in the I/O buffer cell 1ibrary.The clock skew is less than 500ps under 5000 flip-flops at l00MHz on the chip,