0.13/spl mu/m CMOS SOI SP6T antenna switch for multi-standard handsets

Tinella, C.; Richard, Olivier; Cathelin, Andreia; Reaute, F.; Majcherczak, S.; Blanchet, F.; Belot, Didier

doi:10.1109/smic.2005.1587904

Cited by 32 publications

(12 citation statements)

References 3 publications

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“…As shown in the chip photographs reported in [1], [4], [6], [9] and data sheet PE42556 of Peregrine Semiconductor, as the throw count of the antenna switch decreases, the switch driver circuits occupy a larger portion of the total chip area. At the low-throw-count antenna switch side, SOI CMOS-based switches generally occupy a larger chip area, which means larger package size, due to the requirement of the integrated antenna switch driver circuits than GaAs counterparts [18].…”

Section: Resultsmentioning

confidence: 99%

“…Several state-of-the-art techniques such as a floating gate or body method [4], a negative biasing method [5], and a stacked-FET technique [6] have been devised in order to handle a high power signal to 40 dBm under the worst case for antenna impedance mismatch, and therefore recently published SOI CMOS antenna switches adopting these techniques have shown excellent power-handling capability and harmonic distortion performance with small IL [7]- [9]. Nevertheless, there are still some problems to overcome.…”

mentioning

confidence: 99%

“…Due to device downscaling and minimum metal-to-contact (or metal-to-metal) spacing for high integration capability and low cost, the off-capacitances of the switch-FETs are severely affected by BEOL-induced parasitic capacitances as well as front end of line (FEOL)-induced parasitic capacitances. Off-capacitance is given by a sum of FEOL-and BEOL-induced parasitic capacitances (4) where and are the polysilicon gate-to-source/drain overlap capacitances, and are the source/drain-tobulk junction capacitances, is the polysilicon gate-to-sidewall fringing capacitance, and is the source-to-drain capacitance. These are the dominant factors among the FEOL-induced parasitic capacitances.…”

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confidence: 99%

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A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

Kim

et al. 2015

IEEE Trans. Microwave Theory Techn.

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A stacked field-effect transistor (FET) linear cellular antenna switch adopting a transistor layout with odd-symmetrical drain-source metal wiring and an extremely low-power biasing strategy has been implemented in silicon-on-insulator CMOS technology. A multi-fingered switch-FET device with odd-symmetrical drain-source metal wiring is adopted herein to improve the insertion loss (IL) and isolation of the antenna switch by minimizing the product of the on-resistance and off-capacitance. To remove the spurious emission and digital switching noise problems from the antenna switch driver circuits, an extremely low-power biasing scheme driven by only positive bias voltage has been devised. The proposed antenna switch that employs the new biasing scheme shows almost the same power-handling capability and harmonic distortion as a conventional version based on a negative biasing scheme, while greatly reducing long start-up time and wasteful active current consumption in a stand-by mode of the conventional antenna switch driver circuits. The implemented single-pole four-throw antenna switch is perfectly capable of handling a high power signal up to 35 dBm with suitably low IL of less than 1 dB, and shows second-and third-order harmonic distortion of less than 45 dBm when a 1-GHz RF signal with a power of 35 dBm and a 2-GHz RF signal with a power of 33 dBm are applied. The proposed antenna switch consumes almost no static power.Index Terms-Antenna switch, cellular, negative voltage, powerhandling capability, power loss, silicon-on-insulator (SOI), stacked field-effect transistor (FET), switch driver, switch-FET device.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

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confidence: 99%

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A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

Kim

et al. 2015

IEEE Trans. Microwave Theory Techn.

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“…Since high performance antenna switches have already been integrated on SOI [2] and the feasibility of SOI power amplifiers has also been reported very recently [3], we will focus our work on the implementation of harmonic filters on SOI, and then propose a benchmark with IPDs technologies II. HR SOI CMOS TECHNOLOGY DESCRIPTION FEMs require a combination of good isolation, high power/high voltage handling, high efficiency, good passive elements and complementary devices for digital integration.…”

Section: Introductionmentioning

confidence: 99%

Small-size low losses GSM and DCS harmonic filters integrated in a low cost 130 nm high resistivity SOI CMOS technology

Gianesello

Durand

Bon

et al. 2010

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passives functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, GSM and DCS harmonic filters have been achieved in a 130 nm SOI CMOS technology. Measured performances (insertion losses ~1dB and harmonic rejection greater than 30 dB) are clearly competitive with most commercially available Integrated Device Passive (IPD) solutions.Index Terms -SOI, harmonic filter, front end module, high resistivity, integrated passive.

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“…High-resistivity silicon (HRS) substrates are promising for RF applications due to their reduced substrate loss and coupling, which helps to enable RF cellular transmit switches on SOI using HRS handle wafers [1,2]. RF switches have high linearity requirements: for instance, a recent III-V RF switch product specifies less than -45 and -40 dBm for 2 nd and 3 rd harmonic power (H2 and H3), respectively, at +35 dBm input power [3].…”

Section: Introductionmentioning

confidence: 99%

Identification of RF Harmonic Distortion on Si Substrates and its Reduction Using a Trap-Rich Layer

Kerr

Gering

McKay³

et al. 2008

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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Harmonic distortion (HD) is measured arising from coplanar waveguide structures on various substrates at 900 MHz, and significant distortion for silicon substrates is demonstrated for the first time. For an input power of +35 dBm, 2 nd harmonic power of -47 dBm and 3 rd of -57 dBm are measured for a thru calibration structure on oxidized high-resistivity silicon (HRS) substrates, and 2 nd harmonic of -23 and 3 rd of -20 dBm for a longer line on a thinner oxide. These levels are high compared to a full cellular transmit switch product specification of -45 and -40 dBm for 2 nd and 3 rd harmonics, respectively, at similar power levels. The contribution of the silicon substrate to high harmonic levels is investigated experimentally, and an efficient technological solution based on the introduction of a trap-rich layer is demonstrated.

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0.13/spl mu/m CMOS SOI SP6T antenna switch for multi-standard handsets

Cited by 32 publications

References 3 publications

A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

Small-size low losses GSM and DCS harmonic filters integrated in a low cost 130 nm high resistivity SOI CMOS technology

Identification of RF Harmonic Distortion on Si Substrates and its Reduction Using a Trap-Rich Layer

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