This paper describes a design method for complementary metal oxide semiconductor (CMOS) ring oscillators composed of even-stage inverters. First, we propose a quantitative method to evaluate oscillation stability for an even-stage ring oscillator with a CMOS latch. The method uses static noise margin analysis to evaluate the static random access memory (SRAM) cell's data storage stability, by observing the similarity between the oscillator and SRAM cell circuitry. Next, the method is extended to oscillators with multiple latches. Finally, by analyzing oscillation stability using this method, we find that the range of stable oscillation conditions can be drastically widened by adding multiple single-channel latch circuits, and also by an appropriate design of their polarities and insertion positions. We also clarify through Monte Carlo simulations, that the optimized oscillator circuit is robust under process, voltage and temperature fluctuations and device characteristic variations.
This paper describes an analysis of oscillation conditions in CMOS ring oscillators composed of even-stage inverters. A design method optimizing the oscillator's operational margin based on this analysis is also described. We have found that stable oscillation margin analysis for this type of circuit is basically equivalent to the Static Noise Margin (SNM) analysis for SRAM write/read operations. Using this concept, we have established a design method that determines the optimal circuit design parameters to ensure stable oscillation.
Two new parallel bus coding methods for generating a DC-balanced code with additional bits are proposed to achieve the self-stabilization of the intermediate power level in Stacked-Vdd integrated circuits. They contribute to producing a uniform switching current in parallel inputs and outputs (I/Os). Type I coding minimizes the difference in the number of switchings between the upper and lower CMOS I/Os by 8B/10B coding followed by toggle conversion. Type II coding, in which the multi-value running disparity control feature is integrated into the bus-invert coding, requires only one redundant bit for any wider bus. Their DC-balanced feature and the stability effect of the intermediate power level in the Stacked-Vdd structure were experimentally confirmed from the measurement results obtained from the developed test chips.
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